MC9S12VR-Family - Data Sheet - Freescale Semiconductor

MC9S12VR Family Reference Manual, Rev. 2.8
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
waits for additional 256PLLCLK cycles and then samples the RESET pin to determine the originating
source. Table 4-30 shows which vector will be fetched.
Sampled RESET Pin
(256 cycles after
release)
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f VCORST .
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
4.5.2.1 Clock Monitor Reset
Table 4-30. Reset Vector Selection
Oscillator monitor
fail pending
COP
time-out
pending
Figure 4-37. RESET Timing
Vector Fetch
1 0 0 POR
LVR
Illegal Address Reset
External pin RESET
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR
LVR
Illegal Address Reset
External pin RESET
RESET
PLLCLK
S12_CPMU drives S12_CPMU releases
RESET pin low RESET pin
fVCORST fVCORST If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f CMFA (see device electrical characteristics for values), the
Freescale Semiconductor 169
)
(
)
(
512 cycles 256 cycles
)
(
possibly
RESET
driven low
externally