MC9S12VR-Family - Data Sheet - Freescale Semiconductor

High-Side Drivers - HSDRV (S12HSDRV1)
13.1.2 Modes of Operation
The HSDRV module behaves as follows in the system power modes:
1. CPU run mode
The activation of the HSE0 or HSE1 bits enable the related high-side driver. The gate is controlled
by the selected source.
2. CPU stop mode
During stop mode operation the high-side drivers are shut down, i.e. the high-side drivers are
disabled and their gates are turned off The bits in the data register which control the gates (HSDRx)
are cleared automatically. After returning from stop mode the drivers are re-enabled and the state
of the HSE bits are automatically set If the data register bits (HSDRx) were chosen as source in
PIM module, then the respective high-side driver gates stays turned off until the software sets the
associated bit in the data register (HSDRx). When the timer or PWM were chosen as source, the
respective high-side driver gate is controlled by the timer or PWM without further handling When
it is required that the gate stays turned off after the stop mode for this case (PWM or timer), the
software must take the appropriate action to turn off the gate before entering stop mode.
13.1.3 Block Diagram
Figure 13-1 shows a block diagram of the HSDRV module. The module consists of a control and an output
stage. Internal functions can be routed to control the high-side drivers. See PIM chapter for routing options.
HS0 Open Load
HS0 control
HS0 Over Current
HS1 Over Current
HS1 control
HS1 Open Load
Figure 13-1. HSDRV Block Diagram
MC9S12VR Family Reference Manual, Rev. 2.8
VSUPHS
398 Freescale Semiconductor
HS0
HS1