MC9S12VR-Family - Data Sheet - Freescale Semiconductor

2.3.37 Port L Interrupt Enable Register (PIEL)
MC9S12VR Family Reference Manual, Rev. 2.8
Port Integration Module (S12VRPIMV2)
Address 0x026E Access: User read/write 1
1 Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0 0 0
W
2.3.38 Port L Interrupt Flag Register (PIFL)
2.3.39 Port AD Data Register (PT1AD)
PIEL3 PIEL2 PIEL1 PIEL0
Reset 0 0 0 0 0 0 0 0
Figure 2-36. Port L Interrupt Enable Register (PIEL)
Table 2-38. PIEL Register Field Descriptions
Field Description
3-0
PIEL
Pin Interrupt Enable register port L —
This bit enables or disables the edge sensitive pin interrupt on the associated pin. For wakeup from stop mode
this bit must be set.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Address 0x026F Access: User read/write 1
1 Read: Anytime
Write: Anytime, write 1 to clear
7 6 5 4 3 2 1 0
R 0 0 0 0
W
PIFL3 PIFL2 PIFL1 PIFL0
Reset 0 0 0 0 0 0 0 0
Figure 2-37. Port L Interrupt Flag Register (PIFL)
Table 2-39. PIFL Register Field Descriptions
Field Description
3-0
PIFL
Pin Interrupt Flag register port L —
This flag asserts after a valid active edge was detected on the related pin (Section 2.4.4, “Interrupts”). This
can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the
associated interrupt enable bit is set.
1 Active edge on the associated bit has occurred
0 No active edge occurred
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