MC9S12VR-Family - Data Sheet - Freescale Semiconductor

PLL Electrical Specifications
Figure E-2. Maximum Bus Clock Jitter Approximation
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter
to a large extent.
Conditions are shown in Figure A-5 unless otherwise noted
Table E-1. ipll_1vdd_ll18 Characteristics
Num C Rating Symbol Min Typ Max Unit
1 D VCO frequency during system reset f VCORST 8 32 MHz
2 C VCO locking range f VCO 32 50 MHz
3 C Reference Clock f REF 1 MHz
4 D Lock Detection |∆ Lock | 0 1.5 % 1
5 D Un-Lock Detection |∆ unl | 0.5 2.5 % 1
6 C Time to lock t lock
7 C
8 C
J(N)
Jitter fit parameter 12
IRC as reference clock source
Jitter fit parameter 13
XOSCLCP as reference clock source
JN ( )
MC9S12VR Family Reference Manual, Rev. 2.8
150 +
256/f REF
532 Freescale Semiconductor
j1 -------
N
1 5 10 20 N
=
µs
j 1 1.4 %
j 1 1.0 %