MC9S12VR-Family - Data Sheet - Freescale Semiconductor

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LIN Physical Layer (S12LINPHYV1) Reset Shutdown TX: Off, RX: Off LIN pull-up: weak LPE = 0 Normal TX: On, RX: On (full perf) LIN pull-up: strong if LPPUE = 1 weak if LPPUE = 0 STOP and RXONLY = 0 and LPOC=0 Standby TX: Off RX: On (low power) if LPWUE = 1 Off if LPWUE = 0 15.4.3.1 Shutdown Mode LPE = 1 STOP LIN pull-up: strong if LPPUE = 1 weak if LPPUE = 0 LPE = 0 RXONLY=1 or LPOC=1 RXONLY = 0 and LPOC=0 Figure 15-10. LIN Physical Layer Mode Transitions The LIN Physical Layer is fully disabled. No wake-up functionality is available. The internal pull-up resistor is replaced by a high ohmic one (330kΩ) to maintain the LIN Bus pin in the recessive state. Setting LPE at 1 makes the module leave the Shutdown mode to enter the Normal Mode. Setting LPE at 0 makes the module leave the Normal or Receive Only Modes and go back to Shutdown Mode. MC9S12VR Family Reference Manual, Rev. 2.8 Receive Only TX: Off RX: On (full perf) TX: Transmitter RX: Receiver LIN pull-up: strong if LPPUE = 1 weak if LPPUE = 0 436 Freescale Semiconductor STOP LPE = 1 and (RXONLY=1 or LPOC=1) STOP and (RXONLY=1 or LPOC=1)
15.4.3.2 Normal Mode MC9S12VR Family Reference Manual, Rev. 2.8 LIN Physical Layer (S12LINPHYV1) The full functionality is available. Both receiver and transmitter are enabled. Per default (LPPUE = 1), the internal pull-up resistor is the standard LIN slave specified pull-up (30kΩ). If LPPUE = 0, this resistor is replaced by a high ohmic one (330kΩ). If an over-current condition occurs, or if RXONLY is set to 1, the module is leaving the Normal Mode to enter the Receive Only mode. If the MCU goes into stop mode, the LIN Physical Layer goes into Standby Mode. 15.4.3.3 Receive Only Mode This mode has been entered because an over-current condition occurred, or because RXONLY has been set to 1.The transmitter is disabled in this mode. If this mode has been entered because of an over-current condition, RXONLY is set to 1 and can not be cleared till the condition is gone( LPOC=0). The receiver is running in full performance mode in all cases. To return to Normal mode it is mandatory to set the RXONLY bit to 0. Going into stop makes the module leave the Receive Only mode to enter the Standby Mode. 15.4.3.4 Standby Mode with wake-up feature The transmitter of the physical layer is disabled. Like in the Normal and Receive Only Modes, the internal pull-up resistor can be selected to be 30kΩ or 330kΩ to maintain the LIN Bus pin in the recessive state. The receiver enters a low power mode. If LPWUE is set to 0, no wake up feature is available and the Standby Mode has the same electrical properties (current consumption, etc.) as the Shutdown Mode. This allows a low-power consumption when the wake-up feature is not needed. If LPWUE is set to 1 the receiver is able to pass wake-up events to the SCI (Serial Communication Interface). If the LIN is receiving a dominant level longer than t WUFR followed by a rising edge, it will send a pulse to the SCI which generates a wake-up interrupt. Once the MCU exits the stop mode, the LIN Physical Layer is going back to Normal or Receive Only mode depending on the status of the bits LPOC and RXONLY. NOTE Since the wake-up interrupt is requested by the SCI, no wake-up feature is available if the SCI is not used. (For example when using with a timer for bit banging) Freescale Semiconductor 437
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MC9S12VR-Family Reference Manual S1
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Chapter 1 Device Overview MC9S12VR-
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2.3.34 Port L Analog Access Registe
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5.2 External Signal Description . .
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Chapter 9 Pulse-Width Modulator (S1
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12.4.6 Gated Time Accumulation Mode
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16.1.2 Modes of Operation . . . . .
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Appendix H LSDRV Electrical Specifi
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1.3 Chip-Level Features Feature MC9
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1.4.4 Main External Oscillator (XOS
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• Programmable polarity for trans
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1.5 Block Diagram PE0 PE1 VSUP VSS
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Address Module NOTE Reserved regist
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1.6.1 Part ID Assignments MC9S12VR
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1.7.2.7 PS[5:0] — Port S I/O Sign
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1.7.2.21 IOC[3:0] Signals MC9S12VR
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1.8.1 Pinout 48-pin LQFP LGND LIN (
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Package Function 48 LQ FP 32 LQ FP
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1.9 Modes of Operation MC9S12VR Fam
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1.11.2 Interrupt Vectors MC9S12VR F
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MC9S12VR Family Reference Manual, R
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Chapter 2 Port Integration Module (
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Port Pin Name 2.3 Memory Map and Re
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Global Address 0x0243 Reserved 0x02
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Global Address 0x0272 Reserved 0x02
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2.3.3 Port E Data Register (PORTE)
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1 Read: Anytime Write: Anytime Tabl
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2.3.10 Port T Data Register (PTT) M
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2.3.12 Port T Data Direction Regist
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2.3.15 Module Routing Register 0 (M
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Table 2-16. PTS Register Field Desc
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2.3.19 Port S Data Direction Regist
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2.3.21 Port S Polarity Select Regis
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MODRR20 MODRR21 TXD0 0 1 1 0 LPTXD
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Table 2-24. PTP Register Field Desc
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2.3.26 Port P Data Direction Regist
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2.3.29 Port P Polarity Select Regis
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2.3.32 Port L Input Register (PTIL)
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3 PTAENL 1-0 PTAL Table 2-34. PTAL
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2.3.37 Port L Interrupt Enable Regi
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2.3.41 Port AD Data Direction Regis
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2.3.44 Port AD Interrupt Enable Reg
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2.4.3.4 Port S MC9S12VR Family Refe
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Glitch, filtered out, no interrupt
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110K / 550K PIRL=0 / PIRL=1 HV Supp
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Chapter 3 S12G Memory Map Controlle
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3.2 External Signal Description Fig
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Read: Anytime. Write: Only if a tra
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3.3.2.4 Program Page Index Register
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0x0000 0x0400 0x8000 0xC000 0xFFFF
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Chapter 4 S12 Clock, Reset and Powe
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4.1.3 S12CPMU_UHV Block Diagram VSU
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4.2 Signal Description MC9S12VR Fam
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4.3 Memory Map and Registers MC9S12
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4.3.2 Register Descriptions MC9S12V
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Table 4-5. CPMUCLKS Descriptions Fi
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4.3.2.7 S12CPMU_UHV PLL Control Reg
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RTR[3:0] 0000 (÷1) 000 (OFF) OFF 1
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4.3.2.9 S12CPMU_UHV COP Control Reg
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Table 4-14. COP Watchdog Rates if C
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4.3.2.14 Low Voltage Control Regist
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APIES=0 APIES=1 MC9S12VR Family Ref
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4.3.2.18 Reserved Register CPMUTEST
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frequency MC9S12VR Family Reference
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4.3.2.23 Reserved Register CPMUTEST
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4.4.6 System Clock Configurations 4
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Chapter 5 Background Debug Module (
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5.1.3 Block Diagram A block diagram
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Global Address Register Name 0x3_FF
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Register Global Address 0x3_FF06 Fi
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• Hardware BACKGROUND command •
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5.4.5 BDM Command Structure Table 5
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Hardware Read Hardware Write Firmwa
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BDM Clock (Target MCU) Host Drive t
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5.4.9 SYNC — Request Timed Refere
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Chapter 6 S12S Debug Module (S12SDB
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• 4-stage state sequencer for tra
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Address: 0x0021 Reset POR Read: Any
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6.3.2.4 Debug Control Register2 (DB
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6.3.2.6 Debug Count Register (DBGCN
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6.3.2.7.1 Debug State Control Regis
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6.3.2.7.3 Debug State Control Regis
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Address: 0x0028 Read: DBGACTL if CO
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6.3.2.8.2 Debug Comparator Address
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6.3.2.8.6 Debug Comparator Data Low
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6.4.2.1.2 Comparator B MC9S12VR Fam
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RTI ; The execution flow taking int
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Field2 Bits in Normal and Loop1 Mod
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6.5.6 Scenario 5 MC9S12VR Family Re
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Chapter 7 Interrupt Module (S12SINT
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7.2 External Signal Description The
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Chapter 8 Analog-to-Digital Convert
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8.1.2 Modes of Operation 8.1.2.1 Co
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8.2 Signal Description This section
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8.3.2.3 ATD Control Register 2 (ATD
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Table 8-15. Analog Input Channel Se
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3-0 CC[3:0] 8.3.2.8 ATD Compare Ena
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8.3.2.10 ATD Input Enable Register
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8.3.2.12.2 Right Justified Result D
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Chapter 9 Pulse-Width Modulator (S1
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9.3 Memory Map and Register Definit
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Register Name 0x0016 PWMPER2 2 0x00
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9.3.2.2 PWM Polarity Register (PWMP
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9.3.2.6 PWM Control Register (PWMCT
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Module Base + 0x00006 Read: Anytime
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9.3.2.10 PWM Channel Counter Regist
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• The channel is disabled MC9S12V
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Divide by Prescaler Taps: Bus Clock
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9.4.2 PWM Channel Timers MC9S12VR F
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9.4.2.6 Center Aligned Outputs MC9S
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Clock Source 7 Clock Source 5 Clock
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• For channels 0, 1, 4, and 5 the
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Chapter 10 Serial Communication Int
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10.1.4 Block Diagram MC9S12VR Famil
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10.3.2 Register Descriptions MC9S12
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10.3.2.2 SCI Control Register 1 (SC
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10.3.2.3 SCI Alternative Status Reg
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10.3.2.5 SCI Alternative Control Re
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10.3.2.7 SCI Status Register 1 (SCI
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10.3.2.8 SCI Status Register 2 (SCI
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10.4 Functional Description MC9S12V
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10.4.3 Data Format MC9S12VR Family
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10.4.5 Transmitter Bus Clock SBR12:
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10.4.5.5 LIN Transmit Collision Det
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10.4.6.5.2 Fast Data Tolerance MC9S
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10.5.3.1 Description of Interrupt O
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Chapter 11 Serial Peripheral Interf
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SPI Interrupt Request Bus Clock SPI
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11.3.2 Register Descriptions MC9S12
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Table 11-4. SPICR2 Field Descriptio
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5 SPTEF 4 MODF Table 11-8. SPISR Fi
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Receive Shift Register SPIF SPI Dat
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11.4.3.1 Clock Phase and Polarity C
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NOTE Care must be taken when expect
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Chapter 12 Timer Module (TIM16B8CV3
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12.1.3 Block Diagrams PA input inte
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PULSE ACCUMULATOR CHANNEL 7 OUTPUT
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Register Name 0x000E TFLG1 1 0x000F
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12.3.2.3 Output Compare 7 Mask Regi
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Write: Anytime. 12.3.2.10 Timer Int
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Page 389 and 390: ... MC9S12VR Family Reference Manua
Page 391 and 392: 12.4.1 Prescaler MC9S12VR Family Re
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Page 395 and 396: Chapter 13 High-Side Drivers - HSDR
Page 397 and 398: 13.2 External Signal Description Ta
Page 399 and 400: 13.3.2 Register Definition 13.3.3 P
Page 401 and 402: 13.3.5 Reserved Register MC9S12VR F
Page 403 and 404: 13.3.8 HSDRV Interrupt Flag Registe
Page 405 and 406: 13.4.4.1 HSDRV Over Current Interru
Page 407 and 408: Chapter 14 Low-Side Drivers - LSDRV
Page 409 and 410: 14.2 External Signal Description Ta
Page 411 and 412: 14.3.2 Register Definition 14.3.3 P
Page 413 and 414: 14.3.5 Reserved Register MC9S12VR F
Page 415 and 416: 14.3.7 LSDRV Status Register (LSSR)
Page 417 and 418: 14.3.9 LSDRV Interrupt Flag Registe
Page 419 and 420: 14.4.4.1 LSDRV Over Current Interru
Page 421 and 422: Chapter 15 LIN Physical Layer (S12L
Page 423 and 424: IP-BUS LPRXD LPTXD Figure 15-1. LIN
Page 425 and 426: 15.3 Memory Map and Register Defini
Page 427 and 428: 15.3.2.2 LIN Control Register (LPCR
Page 429 and 430: 7 LPSLRWD 1-0 LPSLR[1:0] 15.3.2.5 R
Page 431 and 432: 15.3.2.7 LIN Interrupt Enable Regis
Page 433: NOTE For 20kBit/s and Fast Mode com
Page 437 and 438: 15.5.2 Use Cases 15.5.2.1 LIN Physi
Page 439 and 440: Chapter 16 Supply Voltage Sensor -
Page 443 and 444: 16.3.2.1 BATS Module Enable Registe
Page 445 and 446: 16.3.2.2 BATS Module Status Registe
Page 447 and 448: 16.3.2.5 Reserved Register NOTE The
Page 453 and 454: Chapter 17 64 KByte Flash Module (S
Page 455 and 456: 17.1.2.3 Other Flash Module Feature
Page 459 and 460: P-Flash Memory Map Global Address S
Page 461 and 462: Address & Name 0x0003 FRSV0 0x0004
Page 463 and 464: 6 FDIVLCK 5-0 FDIV[5:0] 17.3.2.2 Fl
Page 465 and 466: The security function in the Flash
Page 467 and 468: Offset Module Base + 0x0005 All ass
Page 469 and 470: Table 17-15. FERSTAT Field Descript
Page 471 and 472: Table 17-19. P-Flash Protection Low
Page 473 and 474: Scenario FLASH START 0x3_8000 0x3_F
Page 477 and 478: 011 100 101 17.3.2.12 Flash Reserve
Page 479 and 480: 17.3.2.17 Flash Reserved5 Register
Page 483 and 484: FCCOB Availability Check Clock Divi
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17.4.4.4 P-Flash Commands MC9S12VR
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17.4.6 Flash Command Description MC
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Table 17-35. Erase Verify P-Flash S
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17.4.6.6 Program Once Command Table
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Table 17-44. Erase Flash Block Comm
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17.4.6.13 Set Field Margin Level Co
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Table 17-59. Erase Verify EEPROM Se
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17.4.7 Interrupts MC9S12VR Family R
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Appendix A MCU Electrical Specifica
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A.1.3 Current Injection MC9S12VR Fa
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A.1.5 ESD Protection and Latch-up I
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A.1.6 Operating Conditions MC9S12VR
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VBAT GND Figure A-2. Supply Current
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A.1.8 I/O Characteristics This sect
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Table A-10. CPMU Configuration for
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Appendix B VREG Electrical Specific
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Appendix C ATD Electrical Specifica
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Supply voltage 3.13 V < V DDA < 5.5
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Supply voltage V DDA =5.12 V, -40 o
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Appendix D HSDRV Electrical Specifi
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Appendix E PLL Electrical Specifica
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Appendix F IRC Electrical Specifica
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Appendix G LINPHY Electrical Specif
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Appendix H LSDRV Electrical Specifi
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Appendix I BATS Electrical Specific
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9 D VSENSE Series Resistor Required
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Appendix J PIM Electrical Specifica
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Appendix K SPI Electrical Specifica
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f SCK /f bus 1/2 1/4 5 Figure K-3.
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In Table K-3. the timing characteri
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Appendix L XOSCLCP Electrical Speci
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Appendix M FTMRG Electrical Specifi
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M.1.1 NVM Reliability Parameters Ta
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Appendix N Package Information MC9S
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Appendix O Ordering Information MC9
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Appendix P Detailed Register Addres
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0x001A-0x001B Part ID Registers MC9
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0x0034-0x003F Clock Reset and Power
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0x0070-0x009F Analog to Digital Con
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0x00A0-0x00C7 Pulse Width Modulator
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0x0120 Interrupt Vector Base Regist
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0x0160-0x0167 LIN Physical Layer (L
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0x0240 -0x027F Port Integration Mod
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0x0280-0x02EF Reserved MC9S12VR Fam
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