MC9S12VR-Family - Data Sheet - Freescale Semiconductor

MC9S12VR Family Reference Manual, Rev. 2.8
S12 Clock, Reset and Power Management Unit (S12CPMU_UHV)
4.3.2.12 S12CPMU_UHV COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
0x003F
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W ARMCOP-Bit
7
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
4.3.2.13 High Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.
Read: Anytime
ARMCOP-Bit
6
ARMCOP-Bit
5
ARMCOP-Bit
4
ARMCOP-Bit
3
ARMCOP-Bit
2
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
ARMCOP-Bit
1
ARMCOP-Bit
0
Reset 0 0 0 0 0 0 0 0
0x02F0
Figure 4-15. S12CPMU_UHV CPMUARMCOP Register
7 6 5 4 3 2 1 0
R
W
0 0
VSEL
0
HTE
HTDS
HTIE HTIF
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-16. High Temperature Control Register (CPMUHTCTL)
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