MC9S12VR-Family - Data Sheet - Freescale Semiconductor

3
PTAENL
1-0
PTAL
Table 2-34. PTAL Register Field Descriptions (continued)
Field Description
NOTE
When enabling the resistor paths to ground by setting PTAL[PTAENL]=1
or by changing PTAL[PTAL1:PTAL0], a settling time of t UNC_HVI + two
bus cycles must be considered to let internal nodes be loaded with correct
values.
MC9S12VR Family Reference Manual, Rev. 2.8
Port Integration Module (S12VRPIMV2)
PorT ADC connection ENable port L —
This bit enables the analog signal link of an HVI pin selected by PTAL[1:0] to an ADC channel. If set to 1 the analog
input function takes precedence over the digital input in run mode by forcing off the input buffers if not overridden by
PTTEL=1.
1 Selected pin by PTAL[1:0] is connected to ADC channel
0 No Port L pin is connected to ADC
PorT ADC connection selector port L —
These selector bits choose the HVI pin connecting to an ADC channel if enabled (PTAENL=1). Refer to Table 2-35
for details.
Table 2-35. HVI pin connected to ADC channel
PTAL[PTAL1] PTAL[PTAL0]
HVI pin connected
to ADC 1
0 0 HVI0
0 1 HVI1
1 0 HVI2
1 1 HVI3
1
Refer to device overview section for channel assignment
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