titus-larsen-titus-1981-apple-interfacing

USER 1
This input will allow you to inhibit the generation of all of the
1/0 SELECT and DEVICE SELECT signals within the Apple computer,
so that you can "turn off' all of the 1/0 devices. This line must
be pulled down to a logic zero to cause this action. To prevent the
accidental use of this line, you must use a wire jumper to connect two
solder pads on the main printed circuit board of the Apple, before
the USER 1 signal can be used. We refer you to the A ple II Reference
Manual for the necessary details.
Since your primary purpose in using the 1/0 SELECT and DE­
VICE SELECT signals is to simplify your interface design, there is
probably no need to use tl;iis line, unless you wish to do some sort of
expansion of the computer system with 1/0 devices that are external
to the basic system, or that might use some of the memory addresses
that have been assigned to the I/ 0 SELECT and DEVICE SELECT
signals. The USER 1 signal is present at pin 39 on the interface connectors.
RDY
There are times when it is necessary to slightly "delay" the 6502
microprocessor so that an external 1/0 device, or memory chip will
have sufficient time to access its data and present it on the data bus.
The ready input ( RDY) found at pin 21 on each of the interface connectors
can be used to put the 6502 in a "wait" condition when it is
grounded. This input must be synchronized with the microprocessor
clock, and it should change its stte during the 1 clock logic one
state. The RDY input was used in older 6502-based computers, since
older memory devices could not access their data as fast as required
by the computer. Thus, when they were addresses, they had to put
the 6502 into a "wait" condition for several clock cycles until their
data was available. We doubt that you will find much use for this
signal, except in specialized interfaces.
Clock Signals
There are six clock signals that are available for interface use.
These are 0, i, Q3, 7M, COLOR_REF, and SYNC. The 0 and
1 are the main timing clock signals, running at 1 MHz. The clock
signals are the inverse of one another. These signals are used to coordinate
external 1/0 operations with the normal flow of data on the
bus. As shown in Fig. 5-12, the 1 signal is used to control the generation
of the RD and WR signals for external 1/0 devices. The I/0
SELECT and DEVICE SELECT signals at the' I/0 connectors have
a"lready been gated, or "qualified," with the cp1 clock signal.
The Q3 signal is a 2 MHz clock signal that is as y mmetric; that is,
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