titus-larsen-titus-1981-apple-interfacing

The actual ORing of these control signals is performed by the
SN74LS20 gate, IC-8. The INPUT REQUEST signal that is output
y this 4-input NAND gate is further gated with OUT and WR. This
ting provides a safety interlock, so that if your breadboard circuits
ave been improperly wired, the bus drivers cannot be placed in the
put mode when an output-type operation is taking place. The reltant
"INPUT REQUEST, BUT NOT OUT OR WR" signal conols
the input/ output mode of the 8216 bus buffers.
Since the Apple generates only the memory write signal, WR, this
imply means that your interface will not be able to tum the bus
.itround for an input operation, when the computer is performing a
rite operation. The OUT signal is used for interfacing with 8080,
85, or Z-80 computers.
Two input ports are shown in Fig. 5-8. Each of these ports is conolled
by a device select pulse that enables the three-state buffers.
is same signal is used as the input request signal, INP REQ, and
ch input port must generate its own input request signal. In this .
ample, the two input request signals have been connected to the
and Z pins at the INP REQ section of the socket at IC-17. It
ould have been just as easy to connect the lines to the X and Y pins.
The use of the interlocking INPUT REQUEST signal, and the asciated
·circuitry only applies to testing interface circuits on the
readboard. If you wish to construct an interface that will directly
lug into the Apple, and that will not use bidirectional bus buffering,
en you will not need to use such an interlock. The main purpose of
is circuitry is to protect your Apple computer from possible dam-
CONNECTIONS TO INPUT REQUEST
TO "W"
TO "Z"
INPUT PORT
DATA
'---+----1----i
DATA BUS
DATA
..._ ____ ,____,
INPUT PORT
Fig. 5·8. Typical input ports showing use of INPUT REQUEST signal.
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