titus-larsen-titus-1981-apple-interfacing

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cal AND pointer. subroutine has been loaded, along with the three-b F.xampie -11·5. A l&imple fis Teoti1111 !'rogrnm 1050 POKE 768,32: POKE 769,PEEK(49321) 1060 Q = USR(O) 1070 IF PEEK(770) = 0 THEN 50 1080 D = PEEK(49320) 1090 . . . Continue here after data input Typical devices that use flags in this way are keyboards, Hopp disks, analog-to-digital converters, and other devices that may pro vide data bytes at irregular periods. In some cases, devices may not the necessary .flag circuit within them for easy :flag control, or they may not generate logic levels that are stable for relatively "long" periods so that they can be properly detected by the computer. In these cases, the "flag" a very short pulse. In fact, some pulses are too short to be tected by the computer, if they are simply input by means of a state input port In cases such as this, it is necessary to design a circuit that "capture" the flag pulse SO that it may be detected the vV,CH!_)UC,JL sometime later. Even if the computer can test a flag bit every milHsecods, it will frequently "miss" short pulses of a few micro" seconds duration. Flip-flop or latch circuits are generally used to remember the ence of flag pulses. Typical flip-fl.op devices are the SN7474 Hip-fl.op, and the SN7476 J-K flip-flop. Most introductory digital tronics books provide a good coverage of flip-flop devices if you to review their operation. A typical flip-Hop-based flag circuit is shown in Fig. 4-7. In circuit, the input device generates a READY pulse that clocks flip-flop, transferring the logic level from the D input to the Q put. The Q output is detected by the computer through the use of input pmt that is separate from the input port that is used for th{) transfer of the eight data bits. The status of the flag bit tested by the computer, as has been described. Once the ne,ces:sai,·y action has taken place, in this case, the input of data device, the flag flip-flop is cleared. A logic zero pulse, plied to the clear input of the flip-flop serves this purpose. While RD 49360 pulse used to control the 8-bit input port could be used to dear the flip-flop, we have shown a separate clear signal, so that the timing relationships can be shown, as in 4-8.
INPUT DEVICE INPUT PORT Dl Dl ' D3 DATA BUS DO READY 1 J"L FLAG PULSE SN7474 1- D Q CK CR J"L t>-J INPUT PORT DO RD49360 J'"L RD49361 L..r ..IL . CLEAR Fig. 4-7. Flip-flop circuit used for detection of flag pulse. n the timing diagram, the READY pulse sets the flip-flop, so that Q output is a logic one. This is detected when the status flag ination is input from port 49361. The logic one state of the flag es the software to perform the steps that input the data byte and clear the flag. The separate CLEAR signal could be generated a POKE command, and appropriate circuitry, although the use e readily available RD 49360 pulse is probably easier. (Q) Fig. 4-8. Flag flip-flop timing .diagram. this example, the flag was tested twice while it was in the logic state. Since this indicated that no new data was ready, no input ers or flag clears were initiated. eral experiments at the end of this book involve the use of flags. 65
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lJ. 21862 APPLE® INTERFACING JONAT
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APPLE® INTERFACING by Jonathan A.
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Preface The purpose in writing this
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make no attempt to provide much det
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Contents CHAPTER 1 6502 PROCESSOR 9
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CHAPTER 1 6502 Processor The Apple
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Fig. 1- 1. 6502 Microprocessor chip
Page 15 and 16: locate the memory "cell" that is to
Page 17 and 18: IR.,view At this point, you should
Page 19 and 20: Gei'!eral-fi!Jrp@S('; I/ 0 Commaru:
Page 21 and 22: of an examined memory location. Fro
Page 23 and 24: will now explore the actions that e
Page 25 and 26: transfers will require more than ei
Page 27 and 28: grams are probably easier to write
Page 29 and 30: ·when the Apple computer is progrn
Page 31 and 32: Y@bie ::!1. VNth i
Page 33 and 34: DECODED OUTPUT puter systems, the R
Page 35 and 36: 1 1 1 Using Decoders In many cases,
Page 37 and 38: used in PEEK commands, for example
Page 39 and 40: An alternate approach is to use bot
Page 41 and 42: sections, but the address inputs, A
Page 43 and 44: fUNCTlON TABLES COMPARING CASCADING
Page 45 and 46: flexible decoding scheme, as shown
Page 47 and 48: until the power is turned off. Ther
Page 49 and 50: the logic zero state. In most cases
Page 51 and 52: ue in sequence (in binary), 255, 25
Page 53 and 54: DATA BUS DATA A SN74125 DATA B DATA
Page 55 and 56: R gates that control the enabling o
Page 57 and 58: state of the unused bits cannot be
Page 59 and 60: CHAPTER 4 Flags and Decisions n alm
Page 61 and 62: VALUE 00111010 00011010 11110000 00
Page 63 and 64: •• Addrss Byte Da;a Syie Mexacl
Page 65: INPUT DEVICE RD 49321 - READY/BUSY
Page 69 and 70: y-language programming will also be
Page 71 and 72: CHAPTER 5 Breadboarding 01 With the
Page 73 and 74: 5 IN4001 (4) 6 ,.___'-'' N:...J LM3
Page 75 and 76: A15 AIO A13 Al2 Al4 All A9 AfJ D .L
Page 77 and 78: In the memory address mode, must pl
Page 79 and 80: PIN CONFIGURATION DJ, LOGIC DIAGRAM
Page 81 and 82: The actual ORing of these control s
Page 83 and 84: Fig. 5·10. Packaged version of the
Page 85 and 86: SIGNAL APPLE PfN INTERFACE PIN +12V
Page 87 and 88: ·.chips have rather slow access ti
Page 89 and 90: are possible, we think that one exp
Page 91 and 92: in most of the experiments unless o
Page 93 and 94: tep 3 You may wish to test other po
Page 95 and 96: ,..,,.,....,"'"' in the block from
Page 97 and 98: None of the outputs should be activ
Page 99 and 100: ---" 2 CLR 20 2 CK Si\17474 The dev
Page 101 and 102: entered and run, It first asks you
Page 103 and 104: +5 Gl\ID LOGIC SWITCHES A B c D 16
Page 105 and 106: PR INT "O"; GOTO 65 If you wish to
Page 107 and 108: am, and the two-byte decimal calcul
Page 109 and 110: for each value that is input to the
Page 111 and 112: of the monitor screen each time the
Page 113 and 114: A = 128 420 B = PEEK(493 l 9) 430 F
Page 115 and 116: il!!lie -2. 0 THEN . . .
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program. You may forgotten steps to
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The A output, RD 49319, has already
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used the following program: FOR A =
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· numbers would have to be "split"
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tep 1 The input port and output por
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0'"""c"y'·i- the relative values t
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and output ports are simply additio
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e has been divided into 256 values,
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e converter will not burn out, sinc
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07 DATA BUS DO 3 4 7 a 13 14 17 18
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each decade. The bed code is used i
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LED BIT RED } D3 YELLOW EL M D4 GRE
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: : FOR T = 0 TO 770 NEX T T NEX T
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Thus, by testing the value input fr
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he six LEDs should be removed from
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Yo'1 should be able to develop the
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INPUT "LAST TWO DIGITS ";A$ IF A$ =
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tfhe program first tests the reset
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would you program the computer so t
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Yes. Simply reverse the commands at
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· computer to measure analog volta
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he minimum value should be in the r
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130 Y2 = PEEK(49319)/ 1.594 140 HPL
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You probably will not see much chan
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D7 D6 D5 D4 D3 D2 Dl DO 'b- • "A"
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ll'i!i Name 1 1/0 SELECT 2- 17 A 15
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ADDRESS BUS A7-AO :> MEMORY 256 x 8
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!n!erfac" Slel Addwess lta"%Je 0 C0
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28 INT IN SLOT 6 +5 lK Lr LOCAL INT
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USER 1 This input will allow you to
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puts. You must be careful in your d
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CONTROL/ DATA input at pin 12 ( C/D
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93427 OR EQUIV ROM ADDRESS BUS 1---
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use of red LEDs is recommended, sin
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APPENDIX B Parts Required for the E
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APPENDIX 6502 Microprocessor Techni
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MC§f.500 IE1lriy {D"i) This input
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MCS6500 INSTilUCTION SH-ALPHABETICA
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,, ,, T!M!NG Il-01! READING DI\ TA
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MCS0t-20 PWH¢01 ns PWH¢2 ¢11ou11
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APPENDIX D Apple Interface Breadboa
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APPENDIX E Printed-Circuit Board Ar
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!'i9. E-2. Printecl-
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F t • I +: a... :::> 0 a: (!> 0 (
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Controllers, 14 Converter analog-to
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Pin configuration-cont SN7474, 150
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The Blacksburg Group According to B
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