titus-larsen-titus-1981-apple-interfacing

·when the Apple computer is progrnmmed to perform a data transfer
using either of the general-purpose I/ 0 commands, PEEK or
POKE, certain signals are generated by the 6502 processor to synchronize
the flow of data. At this point, our main concern is the use
of the address bus lines. These are the 16 lines that address individual
memory locations and I/ 0 devices. You should recall that the
PEEK and POKE instructions each contain decimal address information
that is used to identify the addressed memory location or I/0
device. Of course, the Apple computer has no way of distinguishing
between a memory location and an I/ 0 port
DEVICE ADDIUiSSiNG
Each If 0 device that is to be used with the computer must be able
to recognize its own device address. Since the PEEK and POKE
commands use 16-bit addresses, each If 0 device must monitor these
16 address lines, Al5-AO, for the occurrence of its address. There are
three basic schemes that may be used by I/ 0 device circuits to accomplish
the monitoring for a specific address. These are:
® Gating-detecting a specific combination of logic signals.
® Decoding-a more flexible gating scheme in which many addresses
may be detected.
® Comparing-comparing a preset or known address with the address-bus
signals until a match occurs.
Combinations of these three techniques are possible and there are
probably many variations that are possible. We will describe examples
of each of the three basic address decoding schemes.
lBsillilg Gillies for Addre!ls Dee:@ding
In the scheme for decoding device addresses in which individual
gates are used, the address must be known so that the gates can be
properly configured. In this example, we will use the device address
1010100011110llb or 4325510. Since the binary notation is long, and
somewhat cumbersome, you might feel more comfortable with the
hexadecimal equivalent, A8F7H. Since NAND/ AND gates are the predominant
type of gating logic available, we will use these types of
circuits in our logic.
To refresh your memory, the pin configurations for several types
of AND/NAND gates are shown in Fig. 2-1, with the generalized truth
table for a two-input AND gate and an equivalent NAND gate shown
in Table 2-1. Since inverters such as the SN7404 are often found in
device addressing circuits, a pin configuration for this chip has been
included in Fig. 2-1. The truth tables in Table 2-1 also show the function
of an inverter. In all cases, the logic one state is the higher volt-