titus-larsen-titus-1981-apple-interfacing

logic value of the bus is unknown. Whenever a logic zero is app
to one of the bus buffer enable inputs, the selected buffer passes
data onto the bus. The condition in which more than one buffer
been enabled is not allowed, since bus conflicts will arise.
All of the devices that are to be used with the Apple c.;v•uµutF'J
system to transfer information to the CPU must have three-state o
puts. Thus, even memory chips must have three-state outputs,
they in fact do. The computer designer must be sure that the syst
has been designed so that no two input devices are selected at t
same time. If such a multiple selection takes place, improper ope
tion of the computer occurs.
Input ports that may be used to transfer information to the co
puter are readily constructed using standard three-state integrat
circuits. In most cases, eight individual three-state buffers are us
one per bus line. In most cases, too, the enable inputs are all co
nected in parallel, so that all eight buffers transfer their informati
onto the bus simultaneously. In some cases, the common enabling i
put is provided within the chip so that only a single pin on the chi
is required for the control of all eight bits.
There are many chips that may be used to construct input
but only a few of them are general enough to warrant our cons11ae:ra,
tion. The two main integrated circuits that will be used in our
pies are the SN74365 and the SN74LS244, The SN74365 may also
noted as the DM8095 (National Semiconductor Corp.), which is
exact replacement. The pin configuration for these two chips
shown in Fig. 3-9.
You will note quickly that while the SN74LS244 has eight
state buffers on one chip, the SN74365 has only six. If the
device is used to construct an input port, two of the integrated
packages must be used. A typical 8-bit input port is shown in
3-10. In this case, only two of the three-state buffers in the lower
SN74365 chip have been used. Since the SN74365 contains built-in
SN74lS365
·· :'l-9. !>N74l!i2