titus-larsen-titus-1981-apple-interfacing

DATA DATA DATA DATA
ONE - BIT DATA BUS
bus they are not in use. The input ports must pass logic o
and zeros to the CPU, but they must be configured. so that they
not interfere with the use of the bus when they are not selected.
Depending on the type of gate chosen, simple gates cannot
used to gate data onto the data bus lines since their "unselected" ou
put state will be either a logic one or a logic zero, as shown in F
3-6. Note that even when none of the gates is selected or enabled, t
outputs of the gates are at different logic levels, as noted by t
quoted logic levels. These levels "compete" for the use of the b
probably leading to one or more burned out chips. This shou
clearly illustrate why gates alone are not used on data buses.
Vee 4C 4A 4Y 3A 3Y
l'i. :!l-7. !1174125 b11s i>uffe• d1i1>
pi11 e@rofo91nati11.
1C 1A 1Y 2C 2A 2V GNO
Special integrated circuits with three-state outputs are
to simplify the design of input ports. A typical three-state device
the SN74125 bus buffer, shown in Fig. 3-7. The diagram of the
devices should look familiar. It is simply a buffer (logic one in, logi
one out, etc. ) , but an additional control line, shown
l:o one of the angular sides of the buffer symbol The buffer will
logic ones and zeros from its input to its output when it is vuau'•''
but unlike a simple gate, when it is disabled, the output appears
be electrically disconnected from the or other logic device, to
it is connected. In three-state devices. this third state is often
called the HI-Z or high-impedance state, to note its d.i:scc)rn1e(;te'C1
condition. The disconnecting and connecting is rapid, generally
ing less than 20 nanoseconds.
In the SI"-J7 4125 each three-state buffer has its own
zero for the data to be from the
one state on the enable input forces the
5'.tate. A similar integratsd.