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PIN CONFIGURATION<br />
DJ,<br />
LOGIC DIAGRAM<br />
8216<br />
cs Vee DB0<br />
DO o<br />
DIEN DO ,<br />
DB0<br />
DJ,<br />
oo,<br />
D03<br />
DJ,<br />
DB3<br />
01, oo,<br />
DB 1<br />
os,<br />
oo,<br />
01,<br />
01 ,<br />
OB,<br />
DB 2<br />
GND<br />
01, oo,<br />
PIN NAMES<br />
01 ,<br />
-----() oB,<br />
DB0.oB3<br />
D'o-013<br />
DATA BUS<br />
Bl-DIRECTIONAL<br />
DATA INPUT<br />
000-003 DATA OUTPUT<br />
DIEN<br />
cs<br />
DATA IN ENABLE<br />
DIRECTION CONTROL<br />
CHIP SELECT<br />
set of buffers so that the Apple receives the data properly. Special<br />
.•V with the WR, RD, and RESET signals. The other signals are<br />
< '··>: y;''-'"L" when the breadboard is used with other computers. This concircuitry<br />
is shown in Fig. 5-7. The general-purpose interrupt sigis<br />
also buffered, but it is an input to the computer. Connections<br />
the control signals are made at the socket at IC-17, as noted in<br />
5-4.<br />
The control circuitry also generates a signal that switches the 8216<br />
bus buffers into the input mode, so that data may be transferred into<br />
'fhe Apple. It would seem to be merely a matter of turning the bus<br />
'round whenever a memory read operation took place. If this were<br />
fi:nplemented, the bus buffers on the breadboard would be placed in<br />
the input mode, even when a memory chip was activated within the<br />
pple. This would cause a bus "conflict,'' so the bus on the bread<br />
;oard must be placed in the input mode only when an input device<br />
'<br />
11 the breadboard itself has been selected.
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