titus-larsen-titus-1981-apple-interfacing

the logic zero state. In most cases, the dear input will be connected
to +5 volts (logic one) and v.riH not be used.
Each of the integrated circuits may be used to latch and maintain
the data out by the Apple computer during the execution of a
POKE command. It is a simple matter of using an output device
select pulse to activate the latch circuit once it has been properly
connected to the bus. A typical 8-bit output port is shown in Fig. 3-3.
In this circuit, a logic one output device select pulse is required to
cause i:he latch circuits to acquire and hold the information output
by the Apple.
SN7475
DATA BUS
D7
D6
D5
D4
D3
D2
01
DO
DEVICE SELECT
PULSE
_,,_
2
3
6
7
2
3
6
7
16
D Q
15
0 Q
10
0 Q
9
D Q
G G
l 4 1 13
SN7475
D Q
16
D Q
15
D Q
D Q 9
G G
10
.
D7
D6
D5
04
03
02
DJ
DO
\
DATA
LATCHED
FOR
PERIPHERAL
I
In Fig. 3-4, two SN7 4175 latch chips have been used as an
port, with some sort of logic monitors being used to provide a visual
indication of the information that has been latched by the chipso The
'T' indication at the connections to the CLEAR inputs at the
means that these inputs are connected to +5 volts, or a logic one
The 'T' notation is used to distinguish a level connection
a power-supplying connection, which is noted as +5 or
Vo
An SN7 4LS373 8-bit or octal latch has been used as an
in Fig. 3-5. Only one integrated circuit is
The Output Control line has been
enabledo Again, an