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Starting electronics
The most important consideration is that both inputs of the
SR-type NAND bistable should normally be at logic 1 — this
is in direct contrast with the SR-type NOR bistable, where the
inputs needed to be normally at logic 0. Because of this, the
inputs are considered to be inverted in the circuit, shown as
such in Figure 11.5.
With both inputs of the circuit of Figure 11.5 at logic 1, the
circuit is stable, with both NAND gate outputs at logic 0. When
one input goes to logic 1, the output of that NAND gate goes
to logic 1. This is applied to the other NAND gate’s second
input, so the output of the second NAND gate will go to logic
0. This output is in turn fed to the first NAND gate’s second
input and thus its output is forced to remain at logic 1.
Applying a further logic 0 to the first NAND gate has no further
effect on the circuit — it remains stable. However, when a
logic 0 is applied to the second NAND gate’s input causes the
same reaction in the other direction. So the circuit has two
stable states, hence is a bistable.
Figure 11.6 shows the function table for this SR-type NAND
bistable.
Just as in the SR-type NOR bistable, there is a possibility
that both outputs can be forced to be the same level which
produces an indeterminate outcome. In the SR-type NAND
bistable, this is when both inputs are at logic 0. So, circuit
designers must ensure this situation does not occur in their
logic circuits.
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