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Starting electronics
only change state as the clock signal CLK falls from logic 1 to
logic 0. This change of state from logic 1 to logic 0 is commonly
called the ‘falling edge’, and the overall circuit is generically
known as an ‘edge-triggered’ bistable.
This is an extremely important point in electronic terms. By
creating this master–slave bistable arrangement to make the
bistable edge-triggered, we are able to control precisely when
the bistable changes state. As a benefit, this also makes sure
that there is plenty of time for the master and slave bistables
comprising the overall bistable to respond to the input signals
— although things in logic circuits change and respond
quickly, they do not happen instantly and still do take a finite
time. The master–slave arrangement takes account of and
caters for this small but finite time.
The JK-type bistable
One other problem which we’ve already encountered with
our basic bistables isn’t yet catered for though — the indeterminate
output which can occur in a bistable if both S and
R inputs are logic 1 at the moment when the clock signal falls
from logic 1 to logic 0.
So, to prevent this happening, it’s a matter of preventing both
S and R inputs from being at logic 1 at the same time as the
clock signal falls from logic 1 to logic 0. We do this by adding
some feedback from the slave bistable to the master bistable,
and creating new inputs (labelled J and K).
The circuit of such a JK-type bistable to perform this function
is shown in Figure 11.11.
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