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Digital integrated circuits II
Figure 11.11
A JK-type bistable
As with the edge-triggered master–slave SR-type bistable,
the outputs only change on the falling edge of the clock CLK
signal, so the inputs (J and K now, not S and R) control the
output states at that time. However, the feedback from the
final output stage back to the input stage ensures that one of
the two inputs is always disabled — so the master bistable
cannot change state back and forth while the clock input is
at logic 1. Instead, the enabled input can only change the
master bistable state once, after which no further change of
states can occur.
Because the JK-type bistable is completely predictable in this
manner, under all circuit conditions, the JK-type bistable is the
preferred minimum bistable device for logic circuit designers.
That’s not to say that SR-type bistables can’t be used, and in
fact they do have their purposes, but the important point is
that circuit designers have to be aware of their limitations,
ensuring that unpredictable outcomes are not allowed and
so are designed out of the circuit.
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