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Starting electronics
However, when the and inputs are both high, control
of output becomes the prerogative of the clock and D inputs.
For example, when the clock is low, the output Q = Q 0
. That
is, it remains the same as it was — no matter what the logic
state of the D input (as D = X). On the leading edge of the
clock pulse, however, output Q follows the logic state of the
input D; whether high or low.
JK-type bistable symbol
The JK-type bistable symbol is shown in Figure 11.17, while
its function table is shown in Figure 11.18.
Figure 11.17
A JK-type bistable
Figure 11.18 The function table of a J-K master–slave bistable, such as that
shown in Figure 11.17
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