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Digital integrated circuits II
Figure 11.10
An edge-triggered SR-type NAND bistable
An important component is the the inverter which connects
the two bistables in the circuit. This ensures that the bistables
are enabled during opposite half cycles of the clock signal.
Assuming that the clock input CLK is at logic 0 initially, the
S and R inputs cannot yet affect the master bistable’s operation.
However, when the clock input CLK goes to logic 1 the
S and R inputs are now able to control the master bistable
in the same way they do in Figure 11.8. As the inverter has
inverted the clock signal though, the slave bistable’s inputs
(which are formed by the outputs of the master bistable) now
have no effect on the slave’s outputs. In short, although the
outputs of the master bistable may have changed, they do
not yet have any effect on the slave bistable.
When the clock input CLK falls back to logic 0 the master
bistable once again is no longer controlled by its S and R
inputs. At the same time, however, the inverted clock signal
now allows the slave bistable’s inputs to control the slave
bistable. In other words, the final outputs of the circuits can
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