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[Studies in Computational Intelligence 481] Artur Babiarz, Robert Bieda, Karol Jędrasiak, Aleksander Nawrat (auth.), Aleksander Nawrat, Zygmunt Kuś (eds.) - Vision Based Systemsfor UAV Applications (2013, Sprin

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106 G. Bieszczad et al.<br />

Fig. 13. Tim<strong>in</strong>g diagram of control signals for ULIS’ UL 04 27 2 microbolometer FPA<br />

A special control circuit was designed to read the signals from the particular detectors<br />

<strong>in</strong> an array. Its purpose is to obta<strong>in</strong> for of each detector signal proportional<br />

to <strong>in</strong>cident IR radiation its digital representation. Data is further sent to other camera<br />

blocks by VideoBus l<strong>in</strong>k. All analog detector signals (OUT) need to be<br />

converted <strong>in</strong>to digital form (DVIDEO). Conversion was performed by ADC converter,<br />

which requires clock signal (CLK_VIDEO).<br />

Fig. 14. Tim<strong>in</strong>g diagrm of control signals for ULIS’ UL 04 27 2 microbolometer FPA<br />

Accord<strong>in</strong>g to array catalogue data all control signal can be generated us<strong>in</strong>g s<strong>in</strong>gle<br />

clock signal with MC period. To do this a module was realized with 5-state<br />

mach<strong>in</strong>e and two synchronous counters. First counter is used to determ<strong>in</strong>e the<br />

states of RESET signal and for count<strong>in</strong>g clock cycles dur<strong>in</strong>g the readout of an<br />

entire frame. Second counter is used to determ<strong>in</strong>e the states of INT and MC signals<br />

and performs cycle count dur<strong>in</strong>g s<strong>in</strong>gle row readout. On the basis of RESET,<br />

INT and MC signals the follow<strong>in</strong>g VideoBus signals are simultaneously generated:<br />

VSYNC, HSYNC, STD, MCLK, VDATA. Dur<strong>in</strong>g the operation of UL 04 27<br />

2 microbolometer array the signals on the output of array are delayed by the time<br />

of one row from the <strong>in</strong>tegration trigger signal. This is because at the beg<strong>in</strong>n<strong>in</strong>g of<br />

each frame readout the signals from first row detectors are <strong>in</strong>tegrated. Then, dur<strong>in</strong>g<br />

the readout of first row detectors the signals from second row detectors are<br />

<strong>in</strong>tegrated and the pattern is repeated for the consecutive rows. As a result the total

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