Optimod-AM 9400 V1.2 Operating Manual - Orban

6-10
TECHNICAL DATA ORBAN MODEL 9400
IC211. The purpose of these stages is to reduce the out-of-band noise energy
resulting from the delta-sigma D/A’s noise shaping filter and to translate the
differential output of the D/A converter into single-ended form. These components
apply a 3 rd order low-pass filter to the differential signal from the D/A.
This filter does not induce significant overshoot of the processed audio, which
would otherwise waste modulation.
IC212B and associated components form a low-frequency servo amplifier to
remove residual DC from the signal. The 0.15Hz 3 dB frequency prevents tiltinduced
overshoot in the processed audio.
The buffered output of IC2201 is applied to IC213, a balanced output line
driver. This driver emulates a floating transformer; its differential output level
is independent of whether one side of its output is floating or grounded.
IC213 and its right channel counterpart IC214 are socketed for easy field replacement.
All other circuitry is surface-mounted.
The corresponding right channel circuitry and the circuitry in Analog Output
#2 is functionally identical to that just described.
3. Digital Sample Rate Converters (SRC) and Output Transmitters
Located on Input/Output Daughterboard
For each of the two digital outputs, an integrated output sample rate converter
(SRC) converts the 64 kHz 9400 system output sample rate to any of the standard
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz rates. The SRC chip drives a digital
audio interface transmitter to encode digital audio signals using the AES3 interface
format (AES3-1992). These chips are surface-mounted and are not field replaceable.
DSP Circuit
The DSP circuit consists of eight Motorola DSP56362 24-bit fixed-point DSP chips that
execute DSP software code to implement digital signal processing algorithms.
The algorithms filter, compress, and limit the audio signal. The eight DSP chips, each
operating at approximately 100 million instructions per second (MIPS), for a total of
800MIPS, provide the necessary signal processing. A sampling rate of 32 kHz and
power-of-two multiples thereof, up to 512 kHz, is used.
System initialization normally occurs when power is first applied to the 9400 and can
occur abnormally if the 9400’s watchdog timer forces the SC520 to reboot. Upon initialization,
the SC520 CPU downloads the DSP executable code stored in the flash
memory. This typically takes about 7 seconds. Once a DSP chip begins executing its
program, execution is continuous. The SC520 provides the DSP program with parameter
data (representing information like the settings of various processing controls),
and extracts the front panel metering data from the DSP chips.
During system initialization, the SC520 queries the DSP hardware about its operational
status and will display an error message on-screen if the DSP fails to initialize