TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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Introduction2.3 PGE Package Layout and Pin AssignmentsV SSA22V SSDV DDA10HD7A11A12A13A14A15CV DDHASV SSV SSCV DDHCSHR/WREADYPSDSISR/WMSTRBIOSTRBMSCXFHOLDAIAQHOLDBIOMP/MCDV DDV SSBDR1BFSR1123456789101112131415161718192021222324252627282930313233343536VSS 37144 VSSBCLKR1 38143 A21HCNTL0 39142 CV DDV SS 40141 A9BCLKR0 41140 A8BCLKR2 42139 A7BFSR0 43138 A6BFSR2 44137 A5BDR0 45136 A4HCNTL1 46135 HD6BDR2 47134 A3BCLKX0 48133 A2BCLKX2 49132 A1V SS 50131 A0HINT 51130 DV DDCV DD 52129 HDS2BFSX0 53128 V SSBFSX2 54127 HDS1HRDY 55126 VSSDV DD 56125 CV DDV SS 57124 HD5HD0 58123 D15BDX0 59122 D14BDX2 60121 D13IACK 61120 HD4HBIL 62119 D12NMI 63118 D11INT0 64117 D10INT1 65116 D9INT2 66115 D8INT3 67114 D7CV DD 68113 D6HD1 69112 DV DDV SS 70111 V SSBCLKX1 71110 A20VSS 72109 A19108107106105104103102101100999897969594939291908988878685848382818079787776757473A18A17V SSA16D5D4D3D2D1D0RSX2/CLKINX1HD3CLKOUTV SSHPIENACV DDV SSTMSTCKTRSTTDITDOEMU1/OFFEMU0TOUTHD2HPI16CLKMD3CLKMD2CLKMD1V SSDV DDBDX1BFSX1NOTE: DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins andthe core CPU.The <strong>TMS320VC5409</strong>PGE (144-pin TQFP) package is footprint-compatible with the LC548, LC/VC549, andVC5410 devices.Figure 2−2. PGE Package (Top View)14 SPRS082FApril 1999 − Revised October 2008
Introduction2.4 Terminal FunctionsTERMINALNAMEA22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0The 5409 Terminal Functions table lists each pin name, function, and operating mode(s) for the 5409 device.Some of the 5409 pins can be configured for one of two functions; a primary function and a secondary function.The names of these pins in secondary mode are shaded in grey in Table 2−2.(MSB)(LSB)(MSB)(LSB)INTERNALPIN STATEBus holdersavailable(A15−A0)Bus holdersavailableI/O†O/ZI/O/ZTable 2−2. Terminal FunctionsDATA SIGNALSDESCRIPTIONParallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. Thelower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program,data) or I/O while the upper seven address pins (A22 to A16) are only used to address externalprogram space. These pins are placed in the high-impedance state when the hold mode is enabled,or when OFF is low.Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexedto transfer data between the core CPU and external data/program memory or I/O devices. The databus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted.The data bus also goes into the high-impedance state when OFF is low.The data bus has bus holders to reduce the static power dissipation caused by floating, unusedpins. These bus holders also eliminate the need for external bias resistors on unused pins. Whenthe data bus is not being driven by the 5409, the bus holders keep the pins at the previous logic level.The data bus holders on the 5409 are disabled at reset and can be enabled/disabled via the BH bitof the bank-switching control register (BSCR).† I = Input, O = Output, Z = High-impedance, S = Supply‡ Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs,a buffer is recommended to ensure the VIL and VIH specifications are met.April 1999 − Revised October 2008SPRS082F15
Page 1: TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5: Revision History4 SPRS082FApril 199
Page 6 and 7: ContentsSectionPage5.8 Ready Timing
Page 8 and 9: FiguresFigurePage5−25 McBSP Timin
Page 10 and 11: TablesTablePage5−23 McBSP as SPI
Page 12 and 13: Introduction2 IntroductionThe TMS32
Page 16 and 17: IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19: IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23: Functional Overview15 14 12 11 9 8X
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
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Documentation SupportCLKOUTA[22:0]D
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Documentation Support5.10 Reset, BI
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Documentation Support5.11 Instructi
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Table 5−19. McBSP Transmit and Re
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Documentation Supporttc(BCKRX)tw(BC
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Documentation Support5.13.3 McBSP a
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Documentation SupportTable 5−27.
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Documentation Support5.14 Host-Port
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Documentation SupportHASSecond Byte
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Documentation Support5.14.2 HPI16 M
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Documentation SupportHCStw(DSH)tc(D
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Documentation Support5.15 GPIO Timi
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PACKAGE OPTION ADDENDUMwww.ti.com2-
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MECHANICAL DATAMPBG021C - DECEMBER
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IMPORTANT NOTICETexas Instruments I
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TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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