TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

More documents

Recommendations

Info

Documentation Support5.14.2 HPI16 ModeTable 5−33 and Table 5−34 assume testing over recommended operating conditions and H = 0.5t c(CO) (seeFigure 5−31 through Figure 5−32). In the following tables, DS refers to the logical OR of HCS, HDS1, andHDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shownassuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set, Volume5: Enhanced Peripherals (literature number SPRU302) for additional information.Table 5−33. HPI16 Mode Timing RequirementsMIN MAX UNITtsu(HBV-DSL) Setup time, HAD valid before DS falling edge†‡ 5 nsth(DSL-HBV) Hold time, HAD valid after DS falling edge†‡ 5 nstsu(HAV-DSL) Setup time, HAD valid before DS falling edge† −4H+3 nsth(DSH-HAV) Hold time, address valid after DS rising edge† 1 nstsu(HDV-DSH) Setup time, Dx valid before DS high (HPI write) 3 nsth(DSH-HDV)W Hold time, Dx valid after DS high (HPI write) 2 nstw(DSL) Pulse duration, DS low‡ 20 nstw(DSH) Pulse duration, DS high‡ 10 nsCycle time, DS rising edge to next DS risingedge‡tc(DSH-DSH)(Minimum timings represent WRITEs whilemaximum timings represent READs)† DS refers to the logical OR of HCS and HDS1 and HDS2.‡ Dx refers to any of the HPI data bus pins (D0, D1, D2, etc.).Nonmultiplexed mode (no increment)with no DMA activity.Nonmultiplexed mode (no increment)with 16-bit DMA activity.12H20Hnsns82 SPRS082FApril 1999 − Revised October 2008
Documentation SupportTable 5−34. HPI16 Mode Switching Characteristics †‡§PARAMETER MIN MAX UNITten(DSL-HD) Enable time, Dx driven from DS low 6 19 nstd(DSL-HDV1)Delay time, DS low to Dx valid for anHPI readCase 1a: Memory accesses whenDMAC is active in 16-bit mode andtw(DSH) < 18HCase 1b: Memory accesses whenDMAC is active in 16-bit mode andtw(DSH) ≥ 18HCase 2a: Memory accesses whenDMAC is inactive and tw(DSH) < 10HCase 2b: Memory accesses whenDMAC is inactive and tw(DSH) ≥ 10H18H+19 – tw(DSH)1910H+19 – tw(DSH)Case 3: Register accesses 19th(DSH-HDV)R Hold time, Dx valid after DS rising edge, read 1 8 nstv(HYH-HDV) Valid time, Dx valid before HRDY rising edge 0 6 nstd(DSH-HYL) Delay time, DS or HCS high to HRDY low 10 nstd(DSH-HYH)Delay time, DS high to HRDY high(writes and autoincrement reads)Case 1: Memory access when DMACis active in 16-bit modeCase 2: Memory access when DMACis inactive1918H+1010H+10td(DSL-HYL) Delay time, HDS or HCS low/high to HRDY low/high 10 nstd(COH−HYH) Delay time, CLKOUT high to HRDY high 2 nsNOTE: The HRDY output is always high when the HCS input is high, regardless of DS timings.† DS refers to the logical OR of HCS, HDS1, or HDS2.‡ Dx refers to any of the DPI data bus pins (D0, D1, D2, etc.).§ DMAC stands for direct memory access (DMA) controller. The HPI16 shares the internal DMA bus with the DMAC, thus HPI16 access times areaffected by DMAC activity. GPIO refers to the HD pins when they are configured as general-purpose input/outputs.nsnsApril 1999 − Revised October 2008SPRS082F83
Page 1:
TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5:
Revision History4 SPRS082FApril 199
Page 6 and 7:
ContentsSectionPage5.8 Ready Timing
Page 8 and 9:
FiguresFigurePage5−25 McBSP Timin
Page 10 and 11:
TablesTablePage5−23 McBSP as SPI
Page 12 and 13:
Introduction2 IntroductionThe TMS32
Page 14 and 15:
Introduction2.3 PGE Package Layout
Page 16 and 17:
IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19:
IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21:
IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23:
Functional Overview15 14 12 11 9 8X
Page 24 and 25:
Functional OverviewNO.BITNAMERESETV
Page 26 and 27:
Functional Overview3.2 MemoryThe 54
Page 28 and 29:
Functional Overview3.2.5 Relocatabl
Page 30 and 31:
Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
Page 64 and 65: Documentation SupportCLKOUTA[22:0]D
Page 66 and 67: Documentation Support5.10 Reset, BI
Page 68 and 69: Documentation Support5.11 Instructi
Page 70 and 71: Table 5−19. McBSP Transmit and Re
Page 72 and 73: Documentation Supporttc(BCKRX)tw(BC
Page 74 and 75: Documentation Support5.13.3 McBSP a
Page 76 and 77: Documentation SupportTable 5−27.
Page 78 and 79: Documentation Support5.14 Host-Port
Page 80 and 81: Documentation SupportHASSecond Byte
Page 84 and 85: Documentation SupportHCStw(DSH)tc(D
Page 86 and 87: Documentation Support5.15 GPIO Timi
Page 88 and 89: PACKAGE OPTION ADDENDUMwww.ti.com2-
Page 90: MECHANICAL DATAMPBG021C - DECEMBER
Page 93: IMPORTANT NOTICETexas Instruments I
show all

TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?