TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

5.9 HOLD and HOLDA TimingsDocumentation SupportTable 5−14 and Table 5−15 assume testing over recommended operating conditions and H = 0.5t c(CO) (seeFigure 5−13).Table 5−14. HOLD and HOLDA Timing RequirementsMIN MAX UNITtw(HOLD) Pulse duration, HOLD low 4H+8 nstsu(HOLD) Setup time, HOLD low/high before CLKOUT low 8 nsTable 5−15. HOLD and HOLDA Switching CharacteristicsPARAMETER MIN MAX UNITtdis(CLKL-A) Disable time, address, PS, DS, IS high impedance from CLKOUT low 5 nstdis(CLKL-RW) Disable time, R/W high impedance from CLKOUT low 5 nstdis(CLKL-S) Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 5 nsten(CLKL-A) Enable time, address, PS, DS, IS from CLKOUT low 2H+5 nsten(CLKL-RW) Enable time, R/W enabled from CLKOUT low 2H+5 nsten(CLKL-S) Enable time, MSTRB, IOSTRB enabled from CLKOUT low 1 2H+5 nsValid time, HOLDA low after CLKOUT low 0 4 nstv(HOLDA)Valid time, HOLDA high after CLKOUT low 0 4 nstw(HOLDA) Pulse duration, HOLDA low duration 2H−1 nsCLKOUTHOLDtsu(HOLD)tw(HOLD)tsu(HOLD)HOLDAtv(HOLDA) tv(HOLDA)tw(HOLDA)A[22:0]PS, DS, IStdis(CLKL-A)ten(CLKL-A)D[15:0]R/WMSTRBtdis(CLKL-RW)tdis(CLKL-S)ten(CLKL-RW)ten(CLKL-S)tdis(CLKL-S)ten(CLKL-S)IOSTRBNOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extendedPROGRAM memory.Figure 5−13. HOLD and HOLDA TimingsApril 1999 − Revised October 2008SPRS082F65