TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation Support5.10 Reset, BIO, Interrupt, and MP/MC TimingsTable 5−16 assumes testing over recommended operating conditions and H = 0.5t c(CO) (see Figure 5−14,Figure 5−15, and Figure 5−16).Table 5−16. Reset, BIO, Interrupt, and MP/MC Timing RequirementsMIN MAX UNITth(RS) Hold time, RS after CLKOUT low 0 nsth(BIO) Hold time, BIO after CLKOUT low 0 nsth(INT) Hold time, INTn, NMI, after CLKOUT low† 0 nsth(MPMC) Hold time, MP/MC after CLKOUT low 0 nstw(RSL) Pulse duration, RS low‡§ 4H+4 nstw(BIO)S Pulse duration, BIO low, synchronous 2H+1 nstw(BIO)A Pulse duration, BIO low, asynchronous 4H nstw(INTH)S Pulse duration, INTn, NMI high (synchronous) 2H+1 nstw(INTH)A Pulse duration, INTn, NMI high (asynchronous) 4H nstw(INTL)S Pulse duration, INTn, NMI low (synchronous) 2H+1 nstw(INTL)A Pulse duration, INTn, NMI low (asynchronous) 4H nstw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup 8 nstsu(RS) Setup time, RS before X2/CLKIN low 6 nstsu(BIO) Setup time, BIO before CLKOUT low 7 10 nstsu(INT) Setup time, INTn, NMI, RS before CLKOUT low 8 10 nstsu(MPMC) Setup time, MP/MC before CLKOUT low 8 ns† The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputswith consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that iscorresponding to three CLKOUT sampling sequences.‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronizationand lock-in of the PLL.§ Note that RS may cause a change in clock frequency, therefore changing the value of H. Divide-by-two mode66 SPRS082FApril 1999 − Revised October 2008