TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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Functional OverviewTable 3−7. Pin Control Register (PCR) Bit Field Description (Continued)BITNAMEFUNCTION5 DX STAT DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output.4 DR STAT DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.Receive/Transmit frame synchronization polarity.3FSXP2 FSRP FS(R/X)P = 0 Frame synchronization pulse FS(R/X) is active highFS(R/X)P = 1 Frame synchronization pulse FS(R/X) is active low1 CLKXP0 CLKRPTransmit clock polarityCLKXP = 0CLKXP = 1Receive clock polarityCLKRP = 0CLKRP = 1Transmit data sampled on rising edge of CLKRTransmit data sampled on falling edge of CLKRReceive data sampled on falling edge of CLKRReceive data sampled on rising edge of CLKR34 SPRS082FApril 1999 − Revised October 2008
3.3.2.1 Sample Rate GeneratorFunctional OverviewThe 5409 sample rate generator has four clock input options that are only available when both the PCR andSRGR2 are used. Table 3−8 shows the sample rate generator clock input options.Table 3−8. Sample Rate Generator Clock Input OptionsMODESCLKME(PCR.7)CLKSM(SRGR2.13)CLKS pin 0 0CPU 0 1CLKR pin 1 0CLKX pin 1 115 14 13 12 11 8GSYNC CLKSP CLKSM FSGM FPERR/W-0 R/W R/W R/W R/W7 0LEGEND: R = Read, W = Write, n = value present after resetFPERR/WFigure 3−9. Sample Rate Generator Register 2 (SRGR2)Table 3−9. Sample Rate Generator Register 2 (SRGR2) Bit Field DescriptionsBIT NAME FUNCTIONSample rate generator clock synchronization. Only used when the external clock (CLKS) drives the sample rategenerator clock (CLKSM=0)15 GSYNC14 CLKSPGSYNC = 0GSYNC = 1The sample rate generator clock (CLKG) is free-running.The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame syncsignal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also,frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse.CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock(CLKSM=0).CLKSP = 0CLKSP = 1Rising edge of CLKS generates CLKG and FSG.Falling edge of CLKS generates CLKG and FSG.McBSP sample rate generator clock mode13 CLKSMSCLKME = 0 CLKSM = 0 Sample rate generator clock derived from the CLKS pin(in PCR) CLKSM = 1 Sample rate generator clock derived from CPU clockSCLKME = 1 CLKSM = 0 Sample rate generator clock derived from CLKR pin(in PCR) CLKSM = 1 Sample rate generator clock derived from CLKX pin12 FSGM11 − 0 FPERSample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.FSGM = 0FSGN = 1Transmit frame sync signal (FSX) due to DXR(1/2) copyTransmit frame sync signal driven by the sample rate generator frame sync signal (FSG)Frame period. This determines when the next frame sycn signal should become active. Range: up to 212;1 to 4096 CLKG periods.April 1999 − Revised October 2008SPRS082F35
Page 1: TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5: Revision History4 SPRS082FApril 199
Page 6 and 7: ContentsSectionPage5.8 Ready Timing
Page 8 and 9: FiguresFigurePage5−25 McBSP Timin
Page 10 and 11: TablesTablePage5−23 McBSP as SPI
Page 12 and 13: Introduction2 IntroductionThe TMS32
Page 14 and 15: Introduction2.3 PGE Package Layout
Page 16 and 17: IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19: IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23: Functional Overview15 14 12 11 9 8X
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
Page 64 and 65: Documentation SupportCLKOUTA[22:0]D
Page 66 and 67: Documentation Support5.10 Reset, BI
Page 68 and 69: Documentation Support5.11 Instructi
Page 70 and 71: Table 5−19. McBSP Transmit and Re
Page 72 and 73: Documentation Supporttc(BCKRX)tw(BC
Page 74 and 75: Documentation Support5.13.3 McBSP a
Page 76 and 77: Documentation SupportTable 5−27.
Page 78 and 79: Documentation Support5.14 Host-Port
Page 80 and 81: Documentation SupportHASSecond Byte
Page 82 and 83: Documentation Support5.14.2 HPI16 M
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Documentation SupportHCStw(DSH)tc(D
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Documentation Support5.15 GPIO Timi
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PACKAGE OPTION ADDENDUMwww.ti.com2-
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MECHANICAL DATAMPBG021C - DECEMBER
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IMPORTANT NOTICETexas Instruments I
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