TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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Table 5−19. McBSP Transmit and Receive Timing Requirements † MIN MAX UNITDocumentation Support5.13 Multichannel Buffered Serial Port (McBSP) Timing5.13.1 McBSP Transmit and Receive TimingsTable 5−19 and Table 5−20 assume testing over recommended operating conditions and H = 0.5t c(CO) (seeFigure 5−20 and Figure 5−21).tc(BCKRX) Cycle time, BCLKR/X BCLKR/X ext 4H nstw(BCKRX) Pulse duration, BCLKR/X or BCLKR/X high BCLKR/X ext 2H−1 nsth(BCKRL-BFRH)th(BCKRL-BDRV)th(BCKXL-BFXH)tsu(BFRH-BCKRL)tsu(BDRV-BCKRL)tsu(BFXH-BCKXL)Hold time, external BFSR high after BCLKR lowHold time, BDR valid after BCLKR lowHold time, external BFSX high after BCLKX lowSetup time, external BFSR high before BCLKR lowSetup time, BDR valid before BCLKR lowSetup time, external BFSX high before BCLKX lowBCLKR int 0BCLKR ext 4BCLKR int 0BCLKR ext 4BCLKX int 0BCLKX ext 4BCLKR int 7BCLKR ext 2BCLKR int 7BCLKR ext 2BCLKX int 7BCLKX ext 2tr(BCKRX) Rise time, BCKR/X BCLKR/X ext 8 nstf(BCKRX) Fall time, BCKR/X BCLKR/X ext 8 ns† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal arealso inverted.nsnsnsnsnsns70 SPRS082FApril 1999 − Revised October 2008
Table 5−20. McBSP Transmit and Receive Switching Characteristics †Documentation SupportPARAMETER MIN MAX UNITtc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4H nstw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D−3‡ D+1‡ nstw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C−3‡ C+1‡ nstd(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR int −2 2 nstd(BCKXH-BFXV)tdis(BCKXH-BDXHZ)Delay time, BCLKX high to internal BFSX validDisable time, BCLKX high to BDX high impedance following last data bitBCLKX int 0 6BCLKX ext 4 12BCLKX int −4 7BCLKX ext 3 9Delay time, BCLKX high to BDX valid. This applies to all bits except the first BCLKX int 0 7bit transmitted. BCLKX ext 4 12td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid.§BCLKX int 7nsOnly applies to first bit transmitted when in Data Delay 1DXENA = 0or 2 (XDATDLY=01b or 10b) modesBCLKX ext 12Enable time, BCLKX high to BDX driven.§BCLKX int −4te(BCKXH-BDX) Only applies to first bit transmitted when in Data Delay 1DXENA = 0nsor 2 (XDATDLY=01b or 10b) modesBCLKX ext 2Delay time, BFSX high to BDX valid.§BFSX int 2td(BFXH-BDXV) Only applies to first bit transmitted when in Data Delay 0DXENA = 0ns(XDATDLY=00b) mode.BFSX ext 12Enable time, BFSX high to BDX driven.§BFSX int −1te(BFXH-BDX) Only applies to first bit transmitted when in Data Delay 0DXENA = 0ns(XDATDLY=00b) modeBFSX ext 2† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal arealso inverted.‡ T=BCLKRX period = (1 + CLKGDV) * 2HC=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is evenD=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even§ See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable(DXENA) and data delay features of the McBSP. The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the <strong>TMS320VC5409</strong>.nsnsApril 1999 − Revised October 2008SPRS082F71
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TMS320VC5409 Fixed-PointDigital Sig
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Revision History4 SPRS082FApril 199
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ContentsSectionPage5.8 Ready Timing
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FiguresFigurePage5−25 McBSP Timin
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TablesTablePage5−23 McBSP as SPI
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Introduction2 IntroductionThe TMS32
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Introduction2.3 PGE Package Layout
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IntroductionTERMINALNAMEIACKINT0INT
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IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23: Functional Overview15 14 12 11 9 8X
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
Page 64 and 65: Documentation SupportCLKOUTA[22:0]D
Page 66 and 67: Documentation Support5.10 Reset, BI
Page 68 and 69: Documentation Support5.11 Instructi
Page 72 and 73: Documentation Supporttc(BCKRX)tw(BC
Page 74 and 75: Documentation Support5.13.3 McBSP a
Page 76 and 77: Documentation SupportTable 5−27.
Page 78 and 79: Documentation Support5.14 Host-Port
Page 80 and 81: Documentation SupportHASSecond Byte
Page 82 and 83: Documentation Support5.14.2 HPI16 M
Page 84 and 85: Documentation SupportHCStw(DSH)tc(D
Page 86 and 87: Documentation Support5.15 GPIO Timi
Page 88 and 89: PACKAGE OPTION ADDENDUMwww.ti.com2-
Page 90: MECHANICAL DATAMPBG021C - DECEMBER
Page 93: IMPORTANT NOTICETexas Instruments I
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