TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation Support5.5 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled)The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or fourto generate the internal machine cycle. The selection of the clock mode is described in the clock generatorsection.When an external clock source is used, the frequency injected must conform to specifications listed in thetiming requirements table. Table 5−2 and Table 5−3 assumes testing over recommended operating conditionsand H = 0.5t c(CO) (see Figure 5−3).Table 5−2. Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing RequirementsMIN MAX UNITtc(CI) Cycle time, X2/CLKIN 20 † nstf(CI) Fall time, X2/CLKIN 8 nstr(CI) Rise time, X2/CLKIN 8 nstw(CIL) Pulse duration, X2/CLKIN low 5 nstw(CIH) Pulse duration, X2/CLKIN high 5 ns† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequenciesapproaching 0 Hz.Table 5−3. Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching CharacteristicsPARAMETER MIN TYP MAX UNITtc(CO) Cycle time, CLKOUT 40 2tc(CI)† nstd(CIH-CO) Delay time, X2/CLKIN high to CLKOUT high/low 4 10 17 nstf(CO) Fall time, CLKOUT 2 nstr(CO) Rise time, CLKOUT 2 nstw(COL) Pulse duration, CLKOUT low H−2 H−1 H nstw(COH) Pulse duration, CLKOUT high H−2 H−1 H ns† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequenciesapproaching 0 Hz.tc(CI)tw(CIH)tw(CIL)tr(CI)tf(CI)X2/CLKINtc(CO)td(CIH-CO)tf(CO)tr(CO)tw(COH)tw(COL)CLKOUTFigure 5−3. External Divide-by-Two Clock TimingApril 1999 − Revised October 2008SPRS082F53