TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation SupportTable 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) †MASTER SLAVEMIN MAX MIN MAXUNITtsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high 10 − 12H nsth(BCKXH-BDRV) Hold time, BDR valid after BCLKX high 0 5 + 12H nstsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low 10 nstc(BCKX) Cycle time, BCLKX 32H ns† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) †PARAMETERMASTER‡SLAVEMIN MAX MIN MAXth(BCKXH-BFXL) Hold time, BFSX low after BCLKX high§ T − 4 T + 4 nstd(BFXL-BCKXL) Delay time, BFSX low to BCLKX low D − 5 D + 3 nstd(BCKXL-BDXV) Delay time, BCLKX low to BDX valid − 3 7 6H + 5 10H + 14 nstdis(BCKXH-BDXHZ)Disable time, BDX high impedance following last data bit fromBCLKX highUNITD − 2 D + 3 nstdis(BFXH-BDXHZ)Disable time, BDX high impedance following last data bit fromBFSX high2H + 3 6H + 17 nstd(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H − 2 8H + 17 ns† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.‡ T = BCLKX period = (1 + CLKGDV) * 2HD = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSXand BFSR is inverted before being used internally.CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSPCLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock(BCLKX).BCLKXLSBt su(BFXL-BCKXL)MSBt c(BCKX)t h(BCKXH-BFXL)t d(BFXL-BCKXL)BFSXt dis(BFXH-BDXHZ)t dis(BCKXH-BDXHZ)t d(BFXL-BDXV)t d(BCKXL-BDXV)BDXBit 0 Bit(n-1) (n-2) (n-3) (n-4)t su(BDRV-BCKXH)t h(BCKXH-BDRV)BDRBit 0 Bit(n-1) (n-2) (n-3) (n-4)Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 176 SPRS082FApril 1999 − Revised October 2008