TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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FiguresFigurePage5−25 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . 765−26 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . 775−27 Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805−28 Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815−29 HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815−30 HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815−31 Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845−32 Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855−33 GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 SPRS082FApril 1999 − Revised October 2008
TableList of TablesTablesPage2−1 Pin Assignments for the GGU (144-Pin BGA Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132−2 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153−1 Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223−2 Software Wait-State Configuration Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233−3 Bank-Switching Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243−4 CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253−5 Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273−6 Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313−7 Pin Control Register (PCR) Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333−8 Sample Rate Generator Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353−9 Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 353−10 McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363−11 Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373−12 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423−13 DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423−14 DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433−15 DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433−16 Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453−17 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463−18 IFR and IMR Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475−1 Recommended Operating Conditions of Internal Oscillator With External Crystal . . . . . . . . . . . . . 525−2 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing Requirements . . . . . . . . . . . . 535−3 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching Characteristics . . . . . . . . 535−4 Multiply-By-N Clock Option (PLL Enabled) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 545−5 Multiply-By-N Clock Option (PLL Enabled) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 545−6 Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555−7 Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555−8 Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575−9 Parallel I/O Read Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595−10 Parallel I/O Port Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595−11 Parallel I/O Port Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605−12 Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . 615−13 Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . 615−14 HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655−15 HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655−16 Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665−17 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . . 685−18 External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695−19 McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705−20 McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715−21 McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735−22 McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73April 1999 − Revised October 2008SPRS082F9
Page 1: TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5: Revision History4 SPRS082FApril 199
Page 6 and 7: ContentsSectionPage5.8 Ready Timing
Page 10 and 11: TablesTablePage5−23 McBSP as SPI
Page 12 and 13: Introduction2 IntroductionThe TMS32
Page 14 and 15: Introduction2.3 PGE Package Layout
Page 16 and 17: IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19: IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23: Functional Overview15 14 12 11 9 8X
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59:
Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61:
Documentation Support5.7.4 Parallel
Page 62 and 63:
Documentation SupportCLKOUTA[22:0]D
Page 64 and 65:
Documentation SupportCLKOUTA[22:0]D
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Documentation Support5.10 Reset, BI
Page 68 and 69:
Documentation Support5.11 Instructi
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Table 5−19. McBSP Transmit and Re
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Documentation Supporttc(BCKRX)tw(BC
Page 74 and 75:
Documentation Support5.13.3 McBSP a
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Documentation SupportTable 5−27.
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Documentation Support5.14 Host-Port
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Documentation SupportHASSecond Byte
Page 82 and 83:
Documentation Support5.14.2 HPI16 M
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Documentation SupportHCStw(DSH)tc(D
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Documentation Support5.15 GPIO Timi
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PACKAGE OPTION ADDENDUMwww.ti.com2-
Page 90:
MECHANICAL DATAMPBG021C - DECEMBER
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IMPORTANT NOTICETexas Instruments I
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