TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Functional Overview3.3.5 DMA ControllerThe 5409 direct memory access (DMA) controller transfers data between points in the memory map withoutintervention by the CPU. The DMA controller allows movements of data to and from internal program/datamemory, internal peripherals (such as the McBSPs), and external program/data memory to occur in thebackground of CPU operation. The DMA has six independent programmable channels allowing six differentcontexts for DMA operation.The DMA has the following features:• The DMA has external memory access.• The DMA operates independently of the CPU.• The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.• The DMA has higher priority than the CPU for internal accesses.• Each channel has independently programmable priorities.• Each channel’s source and destination address registers can have configurable indexes through memoryon each read and write transfer, respectively. The address may remain constant, be post-incremented,post-decremented, or be adjusted by a programmable value.• Each internal read or write transfer may be initialized by selected sync events.• Each DMA channel is capable of sending interrupts to the CPU.• The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)3.3.5.1 DMA External AccessThe 5409 DMA supports external accesses to extended program, extended data, and extended I/O memory.These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be usedfor external memory accesses. The DMA external accesses require 9 cycle minimums for external writes and13 cycle minimums for external reads.The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of theexternal bus the other will be held−off via wait states until the current transfer is complete. The DMA takesprecedence over XIO requests. The HOLD/HOLDA feature of the 5409 affects external CPU transfers as wellas external DMA transfers. When an external processor asserts the HOLD pin to gain control of the memoryinterface, the HOLDA signal is not asserted until all pending DMA transfers are complete. To prevent the DMAfrom blocking out the CPU or HOLD/HOLDA feature from accessing the external bus, uninterrupted bursttransfers are not supported by the DMA. Subsequently, CPU and DMA arbitration testing is performed foreach external bus cycle, regardless of the bus activity.• Only two channels are available for external accesses. (One for external reads/one for external writes.)• Single-word (16-bit) transfers are supported for external accesses.• The DMA does not support transfers from peripherals to external memory.• The DMA does not support transfers from external memory to the peripherals.• The DMA does not support external to external transfers.• The DMA does not support synchronized external transfers.The HM bit in the ST1 register indicates whether the processor continues internal execution whenacknowledging an active HOLD signal.• HM = 0, the processor continues execution from internal program memory but places its external interfacein the high impedance state.• HM = 1, the processor halts internal execution.To ensure that proper arbitration occurs, the HM bit should be set to 0 in the memory-mapped ST1 register.If the HM is set to 1 the processor will halt during DMA external transfers.38 SPRS082FApril 1999 − Revised October 2008