TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation Support5.7.4 Parallel I/O Port WriteTable 5−11 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t c(CO) (seeFigure 5−8).Table 5−11. Parallel I/O Port Write Switching Characteristics †PARAMETER MIN MAX UNITtd(CLKL-A) Delay time, CLKOUT low to address valid 0 3 nstd(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low 0 3 nstd(CLKH-D)IOW Delay time, CLKOUT high to write data valid H−5 H+8 nstd(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high 0 3 nstd(CLKL-RWL) Delay time, CLKOUT low to R/W low 0 3 nstd(CLKL-RWH) Delay time, CLKOUT low to R/W high 0 3 nsth(A)IOW Hold time, address valid after CLKOUT low 0 3 nsth(D)IOW Hold time, write data after IOSTRB high H−3 H+7 nstsu(D)IOSTRBH Setup time, write data before IOSTRB high H−7 H+1 nstsu(A)IOSTRBL Setup time, address valid before IOSTRB low H−2 H+2 ns† Address and IS timings are included in timings referenced as address.CLKOUTtd(CLKL-A)tsu(A)IOSTRBLth(A)IOWA[22:0]td(CLKH-D)IOWth(D)IOWD[15:0]td(CLKH-ISTRBL)td(CLKH-ISTRBH)tsu(D)IOSTRBHIOSTRBtd(CLKL-RWL)td(CLKL-RWH)R/WISNOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extendedPROGRAM memory.Figure 5−8. Parallel I/O Port Write60 SPRS082FApril 1999 − Revised October 2008