TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation Support5.13.3 McBSP as SPI Master or Slave TimingTable 5−23 to Table 5−30 assume testing over recommended operating conditions and H = 0.5t c(CO) (seeFigure 5−23, Figure 5−24, Figure 5−25, and Figure 5−26).Table 5−23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) †MASTER SLAVEMIN MAX MIN MAXUNITtsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low 10 − 12H nsth(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 0 5 + 12H nstsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high 10 nstc(BCKX) Cycle time, BCLKX 12H 32H ns† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.Table 5−24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) †PARAMETERMASTER‡SLAVEMIN MAX MIN MAXth(BCKXL-BFXL) Hold time, BFSX low after BCLKX low§ T − 4 T + 4 nstd(BFXL-BCKXH) Delay time, BFSX low to BCLKX high C − 5 C + 3 nstd(BCKXH-BDXV) Delay time, BCLKX high to BDX valid − 3 7 6H + 5 10H + 14 nstdis(BCKXL-BDXHZ)tdis(BFXH-BDXHZ)Disable time, BDX high impedance following last data bit fromBCLKX lowDisable time, BDX high impedance following last data bit fromBFSX highUNITC − 2 C + 3 ns2H+ 3 6H + 17 nstd(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H + 2 8H + 17 ns† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.‡ T = BCLKX period = (1 + CLKGDV) * 2HC = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSXand BFSR is inverted before being used internally.CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSPCLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock(BCLKX).BCLKXLSBt su(BFXL-BCKXH)MSBt c(BCKX)BFSXt h(BCKXL-BFXL)t d(BFXL-BCKXH)t dis(BFXH-BDXHZ)t dis(BCKXL-BDXHZ)t d(BFXL-BDXV)t d(BCKXH-BDXV)BDXBDRBit 0 Bit(n-1) (n-2) (n-3) (n-4)t su(BDRV-BCLXL)t h(BCKXL-BDRV)Bit 0 Bit(n-1) (n-2) (n-3) (n-4)Figure 5−23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 074 SPRS082FApril 1999 − Revised October 2008