TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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Functional OverviewHex0000007F00807FFF8000BFFFC000ProgramReservedDARAMInternal32KOn-ChipROMHex010000017FFF018000ProgramExternalExternalHexxx0000ProgramExternalDataHex0000 Reserved001F0020DRR200021DRR100022DXR200023DXR100024Reserved002F0030DRR220031DRR120032DXR22003300340035003600370038Reserved0039003ARCERA0003BXCERA0003C Reserved003F00400041004200430044DXR12ReservedRCERA2XCERA2DRR21DRR11DXR21DXR11Reserved0049004ARCERA1004BXCERA1004C Reserved005F0060 Scratch-Pad RAM007F0080Hexxx0000DataExternalHex0000I/OExternalDARAM7FFF8000ExternalFFFFNOTE: n = 1, 2, 3, or 401FFFFxxFFFFPage 0 Page nPage 5, 6, ...FFFFxxFFFFFigure 3−10. <strong>TMS320VC5409</strong> DMA Memory MapPage 1, 2, ... 127FFFFPage 0, 1, ... 1273.3.5.4 DMA Priority LevelEach DMA channel can be independently assigned high priority or low priority relative to each other. MultipleDMA channels that are assigned to the same priority level are handled in a round-robin manner.3.3.5.5 DMA Source/Destination Address ModificationThe DMA provides flexible address-indexing modes for easy implementation of data management schemessuch as autobuffering and circular buffers. Source and destination addresses can be indexed separately andcan be post-incremented, post-decremented, or post-incremented with a specified index offset.40 SPRS082FApril 1999 − Revised October 2008
Functional Overview3.3.5.6 DMA in Autoinitialization ModeThe DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registerscan be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, andDMGCR). Autoinitialization allows:• Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after thecompletion of the current block transfer; but with the global reload registers, it can reinitialize these valuesfor the next block transfer any time after the current block transfer begins.• Repetitive operation: The CPU does not preload the global reload register with new values for each blocktransfer but only loads them on the first block transfer.3.3.5.7 DMA Transfer CountingThe DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fieldsthat represent the number of frames and the number of elements per frame to be transferred.• Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximumnumber of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented uponthe last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter isreloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame countof 0 (default value) means the block transfer contains a single frame.• Element count. This 16-bit value defines the number of elements per frame. This counter is decrementedafter the read transfer of each element. The maximum number of elements per frame is 65536(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter isreloaded with the DMA global count reload register (DMGCR).3.3.5.8 DMA Transfers in Double-word Mode (Internal Only)Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, twoconsecutive 16-bit transfers are initiated and the source and destination addresses are automatically updatedfollowing each transfer. In this mode, each 32-bit word is considered to be one element.3.3.5.9 DMA Channel Index RegistersThe particular DMA channel index register is selected by way of the SIND and DIND field in the DMA modecontrol register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 andDMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer isthe last in the current frame. The normal adjustment value (element index) is contained in the element indexregisters DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determinedby the selected DMA frame index register (either DMFRI0 or DMFRI1).The element index and the frame index affect address adjustment as follows:• Element index: For all except the last transfer in the frame, the element index determines the amount tobe added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) asselected by the SIND/DIND bits.• Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment asselected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.April 1999 − Revised October 2008SPRS082F41
Page 1: TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5: Revision History4 SPRS082FApril 199
Page 6 and 7: ContentsSectionPage5.8 Ready Timing
Page 8 and 9: FiguresFigurePage5−25 McBSP Timin
Page 10 and 11: TablesTablePage5−23 McBSP as SPI
Page 12 and 13: Introduction2 IntroductionThe TMS32
Page 14 and 15: Introduction2.3 PGE Package Layout
Page 16 and 17: IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19: IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 22 and 23: Functional Overview15 14 12 11 9 8X
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
Page 64 and 65: Documentation SupportCLKOUTA[22:0]D
Page 66 and 67: Documentation Support5.10 Reset, BI
Page 68 and 69: Documentation Support5.11 Instructi
Page 70 and 71: Table 5−19. McBSP Transmit and Re
Page 72 and 73: Documentation Supporttc(BCKRX)tw(BC
Page 74 and 75: Documentation Support5.13.3 McBSP a
Page 76 and 77: Documentation SupportTable 5−27.
Page 78 and 79: Documentation Support5.14 Host-Port
Page 80 and 81: Documentation SupportHASSecond Byte
Page 82 and 83: Documentation Support5.14.2 HPI16 M
Page 84 and 85: Documentation SupportHCStw(DSH)tc(D
Page 86 and 87: Documentation Support5.15 GPIO Timi
Page 88 and 89: PACKAGE OPTION ADDENDUMwww.ti.com2-
Page 90:
MECHANICAL DATAMPBG021C - DECEMBER
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IMPORTANT NOTICETexas Instruments I
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