TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

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Functional Overview15 14 12 11 9 8XPA I/O DATA DATAR/W-0 R/W-111 R/W-1117 6 5 3 2 0DATA PROGRAM PROGRAMR/W−111 R/W−111 R/W−111LEGEND: R = Read, W = Write, n = value present after resetFigure 3−2. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]Table 3−1. Software Wait-State Register (SWWSR) Bit FieldsBITRESETNO. NAME VALUEFUNCTION15 XPA 0Extended program address control bit. XPA is used in conjunction with the program space fields(bits 0 through 5) to select the address range for program space wait states.14−12 I/O 1I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesseswithin addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 forthe base number of wait states.11−9 Data 1Upper data space. The field value (0−7) corresponds to the base number of wait states for externaldata space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines amultiplication factor of 1 or 2 for the base number of wait states.8−6 Data 1Lower data space. The field value (0−7) corresponds to the base number of wait states for externaldata space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines amultiplication factor of 1 or 2 for the base number of wait states.Upper program space. The field value (0−7) corresponds to the base number of wait states for externalprogram space accesses within the following addresses:5−3 Program 12−0 Program 1XPA = 0: x8000 − xFFFFh XPA = 1: The upper program space bit field has no effect on wait states.The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.Program space. The field value (0−7) corresponds to the base number of wait states for externalprogram space accesses within the following addresses:XPA = 0: x0000−x7FFFh XPA = 1: 00000−FFFFFhThe SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.The software wait-state multiplier bit of the software wait-state configuration register is used to extend the basenumber of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−3 and describedin Table 3−2.22 SPRS082FApril 1999 − Revised October 2008
Functional Overview15 8ReservedR/W-07 1 0ReservedR/W-0SWSMR/W−0LEGEND: R = Read, W = Write, n = value present after resetFigure 3−3. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]Table 3−2. Software Wait-State Configuration Register (SWCR) Bit FieldsPINRESETNO. NAME VALUEFUNCTION15−1 Reserved 0 These bits are reserved and are unaffected by writes.Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factorof 1 or 2.0 SWSM 0 SWSM = 0: wait-state base values are unchanged (multiplied by 1).SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.3.1.2 Programmable Bank-Switching Wait StatesThe programmable bank-switching logic of the 5409 is functionally equivalent to that of the 548/549 devices.This feature automatically inserts one cycle when accesses cross memory-bank boundaries within programor data memory space. A bank-switching wait state can also be automatically inserted when accesses crossthe data space boundary into program space.The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 3−4shows the BSCR and its bits are described in Table 3−3.15 12 11 10 8BNKCMP PS−DS ReservedR/W-1111 R/W−1 R−07 3 2 1 0Reserved HBH BH EXIOR−0 R/W-0 R/W-0 R/W-0LEGEND: R = Read, W = Write, n = value present after resetFigure 3−4. Bank-Switching Control Register (BSCR) [MMR Address 0029h]April 1999 − Revised October 2008SPRS082F23
Page 1: TMS320VC5409 Fixed-PointDigital Sig
Page 4 and 5: Revision History4 SPRS082FApril 199
Page 6 and 7: ContentsSectionPage5.8 Ready Timing
Page 8 and 9: FiguresFigurePage5−25 McBSP Timin
Page 10 and 11: TablesTablePage5−23 McBSP as SPI
Page 12 and 13: Introduction2 IntroductionThe TMS32
Page 14 and 15: Introduction2.3 PGE Package Layout
Page 16 and 17: IntroductionTERMINALNAMEIACKINT0INT
Page 18 and 19: IntroductionTERMINALNAMEINTERNALPIN
Page 20 and 21: IntroductionTERMINALNAMETCKTDITDOTM
Page 24 and 25: Functional OverviewNO.BITNAMERESETV
Page 26 and 27: Functional Overview3.2 MemoryThe 54
Page 28 and 29: Functional Overview3.2.5 Relocatabl
Page 30 and 31: Functional OverviewThe HPI8/16 func
Page 32 and 33: Functional Overview3.3.2 Multichann
Page 34 and 35: Functional OverviewTable 3−7. Pin
Page 36 and 37: Functional Overview3.3.2.2 McBSP Co
Page 38 and 39: Functional Overview3.3.5 DMA Contro
Page 40 and 41: Functional OverviewHex0000007F00807
Page 42 and 43: Functional Overview3.3.5.10 DMA Int
Page 44 and 45: Functional OverviewTable 3−15. DM
Page 46 and 47: Functional Overview3.4 InterruptsVe
Page 48 and 49: Documentation Support4 Documentatio
Page 50 and 51: Documentation Support5 Electrical S
Page 52 and 53: Documentation Support5.4 Internal O
Page 54 and 55: Documentation Support5.6 Multiply-B
Page 56 and 57: Documentation SupportCLKOUTtd(CLKL-
Page 58 and 59: Documentation SupportCLKOUTtd(CLKL-
Page 60 and 61: Documentation Support5.7.4 Parallel
Page 62 and 63: Documentation SupportCLKOUTA[22:0]D
Page 64 and 65: Documentation SupportCLKOUTA[22:0]D
Page 66 and 67: Documentation Support5.10 Reset, BI
Page 68 and 69: Documentation Support5.11 Instructi
Page 70 and 71: Table 5−19. McBSP Transmit and Re
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Documentation Supporttc(BCKRX)tw(BC
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Documentation Support5.13.3 McBSP a
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Documentation SupportTable 5−27.
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Documentation Support5.14 Host-Port
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Documentation SupportHASSecond Byte
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Documentation Support5.14.2 HPI16 M
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Documentation SupportHCStw(DSH)tc(D
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Documentation Support5.15 GPIO Timi
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PACKAGE OPTION ADDENDUMwww.ti.com2-
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MECHANICAL DATAMPBG021C - DECEMBER
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IMPORTANT NOTICETexas Instruments I
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