TMS320VC5409 Fixed-Point Digital Signal ... - Texas Instruments

Documentation Support5.11 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) TimingsTable 5−17 assumes testing over recommended operating conditions and H = 0.5t c(CO) (see Figure 5−17).Table 5−17. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching CharacteristicsPARAMETER MIN MAX UNITtd(CLKL-IAQL) Delay time, CLKOUT low to IAQ low 0 3 nstd(CLKL-IAQH) Delay time, CLKOUT low to IAQ high 0 3 nstd(A)IAQ Delay time, address valid to IAQ low 1 nstd(CLKL-IACKL) Delay time, CLKOUT low to IACK low 0 3 nstd(CLKL-IACKH) Delay time , CLKOUT low to IACK high 0 3 nstd(A)IACK Delay time, address valid to IACK low 1 nsth(A)IAQ Hold time, IAQ high after address invalid − 2 nsth(A)IACK Hold time, IACK high after address invalid − 2 nstw(IAQL) Pulse duration, IAQ low 2H−2 nstw(IACKL) Pulse duration, IACK low 2H−2 nsCLKOUTA[22:0]td(CLKL-IAQL)td(A)IAQtd(CLKL-IAQH)th(A)IAQIAQtw(IAQL)td(CLKL-IACKL)td(A)IACKtd(CLKL-IACKH)th(A)IACKIACKtw(IACKL)MSTRBNOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extendedPROGRAM memory.Figure 5−17. IAQ and IACK Timings68 SPRS082FApril 1999 − Revised October 2008