research activities in 2007 - CSEM
research activities in 2007 - CSEM
research activities in 2007 - CSEM
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High Dynamic Range Versatile Front-End for Vision Systems<br />
P. Heim, F. Kaess, P.-F. Rüedi<br />
A 128 by 152 pixel array with very high <strong>in</strong>tra-scene dynamic range has been <strong>in</strong>tegrated <strong>in</strong> a 0.18 µm optical process. It features a data<br />
representation which encodes nearly 7 decades of illum<strong>in</strong>ation with a 10 bit data word. Furthermore, the data representation used facilitates<br />
subsequent data process<strong>in</strong>g such as contrast computation.<br />
There is an <strong>in</strong>creas<strong>in</strong>g need for optical sensors optimally<br />
suited for systems whose purpose is not to restitute an image<br />
to a f<strong>in</strong>al user, but to analyze the content of a visual scene<br />
and make a decision. The ma<strong>in</strong> requirements for such a<br />
sensor are a wide <strong>in</strong>tra-scene dynamic range and a data<br />
representation facilitat<strong>in</strong>g process<strong>in</strong>g. Standard image sensors<br />
have a too narrow dynamic range to cope with the<br />
tremendous change of illum<strong>in</strong>ation occurr<strong>in</strong>g <strong>in</strong> natural visual<br />
scenes. Logarithmic imagers offer a wide dynamic range and<br />
a data representation which easily discard illum<strong>in</strong>ation<br />
changes <strong>in</strong> an image. However, up to now, the logarithmic<br />
compression has been performed <strong>in</strong> the analog doma<strong>in</strong>,<br />
br<strong>in</strong>g<strong>in</strong>g a high pixel-to-pixel fixed pattern noise, which makes<br />
them unusable for commercial applications.<br />
The visual front-end developed at <strong>CSEM</strong> circumvents this<br />
issue. It <strong>in</strong>corporates a high dynamic range pixel array with<br />
logarithmic compression <strong>in</strong> the digital doma<strong>in</strong> to avoid the<br />
large fixed pattern noise associated with analog compression.<br />
Figure 1 shows a block diagram of a pixel and the logarithmic<br />
time generator. Each pixel <strong>in</strong>tegrates the photocurrent<br />
delivered by a photodiode on a capacitor. The result<strong>in</strong>g<br />
voltage is cont<strong>in</strong>uously compared to a reference voltage<br />
(VREF). Once VREF is reached, the content of a 10-bit digital<br />
word distributed to all pixels <strong>in</strong> parallel is stored <strong>in</strong> the pixel<br />
memory. This digital word evolves over time to code the<br />
logarithm of the time elapsed s<strong>in</strong>ce the beg<strong>in</strong>n<strong>in</strong>g of the<br />
<strong>in</strong>tegration. Once photo-current <strong>in</strong>tegration is term<strong>in</strong>ated, the<br />
10-bit words stored <strong>in</strong> the pixel array are read-out.<br />
Figure 1: Block diagram of the pixel and logarithmic time generator<br />
The data representation delivered by the sensor enables to<br />
easily discard illum<strong>in</strong>ation and compute the contrast between<br />
neighbour<strong>in</strong>g pixels.<br />
The circuit encompasses an array of 128 by 152 pixels, with a<br />
pixel pitch of 14 µm and a fill factor of 20% <strong>in</strong> a 0.18 µm<br />
optical process. Figure 2 shows a microphotograph of the<br />
circuit.<br />
Figure 2: Micrograph of the circuit<br />
The left of Figure 3 shows an image acquired with the sensor.<br />
Notice that the face of the person and the outside background<br />
are simultaneously visible, illustrat<strong>in</strong>g the high dynamic range.<br />
The right of Figure 3 shows the contrast representation<br />
obta<strong>in</strong>ed by simply comput<strong>in</strong>g the difference between<br />
neighbor<strong>in</strong>g pixels. Notice the <strong>in</strong>dependence on the<br />
illum<strong>in</strong>ation level.<br />
Figure 3: High dynamic range visual scene<br />
A system-on-chip [1] <strong>in</strong>corporat<strong>in</strong>g a 320 by 240 (QVGA) pixel<br />
array based on this pr<strong>in</strong>ciple, an icyflex [2] processor, RAM and<br />
communication <strong>in</strong>terfaces is now <strong>in</strong> the process of be<strong>in</strong>g<br />
<strong>in</strong>tegrated. It will enable vision applications (image capture<br />
and process<strong>in</strong>g) to be performed on a s<strong>in</strong>gle chip.<br />
[1] C. Arm, et al., “icycam , a System-On-Chip (SoC) for Vision<br />
Applications”, <strong>in</strong> this report, page 30<br />
[2] M. Morgan, et al., “icyflex, a Low Power 32-bit Microcontroller<br />
Core”, <strong>CSEM</strong> Scientific and Technical Report 2006, page 20<br />
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