research activities in 2007 - CSEM

Direct Modulation RF Transmitter and Super-Heterodyne Low-IF Receiver Development
Platform for 868 MHz and 915 MHz ISM Bands
M. Contaldo, E. Le Roux, D. Ruffieux, P. Volet, M. Kucera, N. Raemy, F. Giroud, F. Pengg, S. Gyger, C. Arm, P. Heim, F. Kaess,
V. Peiris
This paper presents the design of a radio development platform suited for developing ultra low-power high-performance narrow-band RF
transceivers. In particular, this platform will be used for validating an 868 MHz/915 MHz RF IC featuring up to ±200kHz modulation bandwidth for
different constant-envelope modulation schemes, and consuming below 3 mA current in receive mode under a very-low 1 V supply.
For wireless sensor networks or body-area networks for biomedical
and lifestyle applications, the need of a miniature and
ultra-low power radio transceiver is mandatory to achieve
multi-year autonomy with un-obtrusive embodiment.
Ultra low-power consumption (below 3 mA under 1 V supply in
receive mode) has been demonstrated for radios operating in
sub-GHz bands and using simple FSK/OOK modulation
schemes [1] . On the other hand, the requirements in terms of
modulation schemes and bandwidths happen to differ
significantly depending on the targeted applications. The
design of an optimal radio architecture remains thus a
complex task as the impact and the added value of various
modulation strategies must be quantified carefully before final
integration, in particular for low-power radios.
Although high- and low-level simulations help for preliminary
validation, a given radio architecture may be fully validated
only with real-world measurements including complex channel
and interference situations which are difficult to simulate. To
address this issue, this paper presents an intermediate
approach, in the form of a microelectronics-oriented hardware
development platform, as depicted in Figure 1.
Figure 1: Development platform block diagram
This approach with a programmable FPGA-based back-end
enables the development and validation of various modulation
schemes with a high degree of flexibility, by programming
baseband processing algorithms into the FPGA, and
characterizing the link performance before full integration.
Because the front-end is a low-power RF IC, the architecture
of the platform is very close to that of an integrated circuit.
Hence the design of a complete transceiver combining both
sections on a single die will be enabled with a low risk level.
The RF front-end IC includes the transmitter (Tx), receiver
(Rx) and frequency synthesizer (PLL) circuitry, from the
antenna input towards the analog baseband, without relying
on any other external active components. The Rx/Tx is
designed for operation in the 868/915 MHz bands. The FPGA
embeds the digital parts such as the modulation/demodulation
section of the radio, the control for the RF front-end IC and the
interfaces. For the slow digital configuration signals, e.g.
analog sub-block bias settings, the configuration is done
through serial link (I2C). For fast digital signal, i.e. the RF
synthesizer settings, the configuration is done through a
parallel bus. The FPGA clock signal is generated on the RF
front-end IC, therefore their association does not need any
additional circuit.
Within the RF front-end IC, the transmitter is based on a direct
modulation architecture. The frequency synthesizer is
implemented by means of a fractional-N PLL employing a
3rd order MASH sigma delta modulator, taking advantage of its
beneficial noise shaping effect. The external loop filter and the
programmable charge pump permit a good customizability of
the synthesizer performances. The synthesized signal is then
directly coupled to the power amplifier and directed to a SAW
filter, before reaching the antenna. The receiver is based on a
heterodyne low-IF architecture that down-converts the RF
signal into at 96-103 MHz intermediate frequency and then to
75-150 kHz, where it can be filtered. The signal is then
converted in the digital domain using an integrated
phase-ADC whose output drives the FPGA to allow the design
and measurement of different demodulations [2]
The main specifications of the radio are up to ±200 kHz
modulation bandwidth, with a 3 mA current consumption in Rx
for -105 dBm sensitivity, and 40 mA in Tx for a 10 dBm output
power, under 1V supply. A photograph of the RF front-end IC,
integrated in 0.18um CMOS, is given in Figure 2.
Figure 2: Microphotograph of the RF front-end IC
[1] V. Peiris, et al., “A 1V 433/868MHz 25kb/s-FSK 2kb/s-OOK RF
Transceiver SoC in Standard Digital 0.18 μm CMOS,” in Int.
Solid-State Circ. Conf. Dig. of Tech. Papers, Feb. 2005, 258-259
[2] E. Le Roux, “Low Power Flexible Digital Demodulator for
Integrated RF Transceiver”, CSEM Scientific and Technical
Report 2006, page 27
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