research activities in 2007 - CSEM

Programmable Multi-Processor Engine for Ultra-Low-Power Single-Chip DVB Receiver
C. Arm, P.-D. Pfister, F. Rampogna, Ch. Ruppert • , A. Duret •
A family of System-On-Chip (SoC) circuits implementing terrestrial mobile digital TV (DVB-T/H) receivers as single-die solutions requiring very few
external components has been developed and is being produced by the industrial partner of this project. The use of ultra-low-power programmable
DSPs for the implementation of the Orthogonal Frequency Division Multiplex (OFDM) demodulation and adaptive channel estimation/correction
allows an automatic adaptation of the receiver to the fast-changing reception conditions encountered in mobile receivers
CSEM is participating in a CTI/KTI project whose goal is to
develop modem core intellectual property (IP) supporting
multiple broadband wireless OFDM modulations (DAB, DVB,
T-DMB, MediaFlo, etc.). The core is architectured as a
software defined radio implementing a multiprocessor
architecture based on CSEM Macgic ® DSP core [1] .
The final goal for the industrial partner [2] of this project is the
production of a family of low-cost, low voltage, ultra-low power
single-die digital television receivers in advanced CMOS
technologies (90 nm and smaller geometries). The first
member of this family is the AS-101, which targets the
following ETSI [3] standards:
• DVB-T, Digital Video Broadcasting for low-power
terrestrial digital television receivers
• DVB-H, for mobile ultra-low-power multimedia receivers.
The low power consumption, of less than 325 mW for DVB-T
reception, together with the small footprint, less than 100 mm2 for a complete module, a very short bill of material, and a
choice of standard host interfaces (USB2.0, SDIO, SPI) make
them ideal for a very wide range of mobile consumer
applications.
The structure of the AS-101 DVB receiver chip is shown in
Figure 1. The circuit implements a multiband zero
intermediate frequency RF-tuner, the reprogrammable OFDM
engine made of multiple Macgic ® DSP cores and hardware
accelerators, the channel decoding and the link layer data
stream extraction using a standard 32-bit processor core
together with error correction hardware accelerators.
Figure 1: AS-101 Single-die 90 nm DVB-T/H receiver structure
Two other circuits are members of this family of low-power
OFDM receivers: the AS-102 limited to the support of the
DVB-T standard, and the AS-103 which improves the
reception in difficult conditions by allowing antenna (spatial)
diversity (use of multiple reception antennas).
The CSEM has developed the Macgic ® DSP architecture. The
DSP has been specially tailored and optimized to best suit
OFDM demodulation and channel estimation/correction
algorithms. New instructions and specific operations have
been added; some others, irrelevant to the targeted
application, removed from the instruction set, so as to
optimise its speed and energy consumption.
The software defined radio technology (SDR) architecture,
based on the Macgic ® cores, is a key element of ensuring
quality of service. In addition, the flexibility of CSEM
programmable technology allows adaptive data processing to
therefore guarantee the best performance in all reception
conditions. Our innovative DSP based approach provides the
flexibility to select the most appropriate algorithm in many
circumstances and conditions, and in particular to recover
weak signals in a noisy environment or compensate for the
Doppler effect.
Adaptive channel correction algorithms have been devised
and implemented. These algorithms improve the
demodulation signal-to-noise ratio and therefore reduce the bit
error rate under the most common adverse mobile reception
conditions:
• Multipath: Single-frequency networks where more than
one transmitter broadcasts the same stream, and/or
multiple electromagnetic obstacles/mirrors such as
buildings (and walls/windows when used indoors) that
scatter and/or reflect the broadcast signal, may lead to
potentially destructive interferences, depending on the
spatial location of the receiver. Such interferences can be
countered through antenna diversity.
• Fast changing reception conditions caused by moving
receiver or obstacles, which are typical in urban areas.
• Doppler effect that is caused by fast-moving objects:
typically a mobile receiver located in a car/train.
Prototypes and demonstrators have been developed and have
been available for more than one year. The AS-101 circuit has
entered the production stage and has already been licensed
to a few customers of the industrial partner.
The project partners are Abilis Systems and HEIG-VD [4] .
This work was partly funded by the CTI/KTI which CSEM
thanks.
•
Abilis Systems
[1] F. Rampogna, et al., “FPGA Prototyping Platform for the
Macgic DSP Cores”, CSEM Scientific and Technical Report
2003, page 27
[2] www.Abiliss.com
[3] www.etsi.org/WebSite/Technologies/DVB.aspx
[4] www.heig-vd.ch
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