research activities in 2007 - CSEM

A High-Performance 2.4 GHz RF Front-End in a 90 nm Process
M. Kucera, N. Scolari, F. Pengg, P. Persechini , D. Ruffieux, A. Vouilloz, E. Vardarli, P. Ferrat, J. Chabloz, R. Caseiro, C. Monneron
The ever ongoing advances in semiconductor manufacturing and the continuous shrink of the integrated transistors pose new challenges and
require innovative solutions for the design of high-performance and low-power RF circuits in the ultra-deep submicron range. This paper provides
insight in the design of a high performance 2.4 GHz RF front-end in 90 nm CMOS.
The well known “Moore’s Law” has been valid for nearly 40
years, confirming that integrated circuit (IC) technology
evolves every 18 months with a new process generation that
enables higher circuit integration and reduced IC size and
cost. While the main driving forces are large digital ICs,
analog and RF circuits can also benefit from these technology
advances, in particular system-on-chip (SoC) realizations
where they are embedded jointly with large digital sections
(e.g. mobile telephony ICs).
Concerning radio SoCs, the co-integration of highperformance
low-power RF circuits together with digital blocks
has been proven using submicron CMOS
(0.5µm - 0.18µm) [1] . RF-platforms of the next generation,
such as Software Defined Radios (SDR), rely heavily on large
digital processing blocks [2] , which pleads for using ultra-deep
submicron (UDSM) CMOS (90 nm and beyond). The
challenge today thus consists of the design of highperformance
RF circuits with competitive sizes of the RF
blocks (UDSM CMOS being expensive) and with low power
consumption, which is critical for portable, battery operated
applications targeted by CSEM.
Within this context, CSEM has designed a 90 nm CMOS RF
front-end circuit with the following goals:
• To achieve high-performance specifications with lowest
possible power consumption while minimizing the required
silicon area.
• To design in a standard digital 90 nm CMOS process,
without relying on costly RF/analog processing options:
this is mandatory for enabling seamless co-integration
with digital circuits.
• To establish a library of optimized RF passive devices: the
generic RF passive devices (inductors, capacitors,
varicaps, etc) provided by silicon foundries usually have
inadequate performance and prohibitive sizes, or require
additional processing options. The design of optimized
passives on the standard digital technology is crucial for
achieving best-in-class RF performance.
The RF front-end targets the 2.4 GHz ISM band, and includes
a receiver front-end (LNA, down-conversion mixers), a
transmitter front-end (PA, up-conversion mixers), and the
critical blocks of the frequency synthesizer (RF VCO, LO
buffers, pre-scalers and multi-modulus dividers). The target
specifications are a noise figure of 2 dB for the receiver frontend
with high linearity (IIP3 up to -13 dBm for an entire
receiver), and a current consumption of 8 mA from a 1.6 V
supply. The transmitter targets +27 dBm of output power
which requires the handling of about 1 W and 500 mA on-chip.
The layout of the RF front-end IC is shown in Figure 1.
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Figure 1: Layout of the 2.4 GHz RF front–end in 90nm CMOS
As mentioned above, special care was taken in the design
and modelling of dedicated passives using the methodology
developed at CSEM [3] . A close-up view of one of the RF
inductors together with its RF test-fixture is given in Figure 2.
An inductance value of 12 nH and a quality factor Q better
than 10 at 2.4 GHz are expected. It occupies a surface of
200x200 µm 2 (in the foundry design kit, no inductances were
available without using RF options and limited metal layers).
Figure 2: Layout of an inductor in 90nm (right) with the pad structure
for the device measurement on the RF prober (left)
The 2.4GHz RF front-end presented in this paper is currently
in fabrication and samples for characterization are expected
shortly.
[1] V. Peiris, et al., “A 1V 433/868MHz 25kb/s-FSK 2kb/s-OOK RF
Transceiver SoC in Standard Digital 0.18 μm CMOS,” in Int.
Solid-State Circ. Conf. Dig. of Tech. Papers, Feb. 2005,
258–259.
[2] E. Le Roux, “Low Power Flexible Digital Demodulator for
Integrated RF Transceiver”, CSEM Scientific and Technical
Report 2006, page 27
[3] F. Giroud, et al., “Integrated Inductors in 0.18 μm CMOS and
Model-Fitting Approach for Low-power 2.45GHz RF blocks”,
CSEM Scientific and Technical Report 2005, page 23