Logic selection guide 2016

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SCHMITT TRIGGERS Features and benefits 4 Transform slowly changing input signals into sharply defined, jitter-free output signals 4 Improve noisy signals 4 Reshape signals in complex layouts 4 Mixed 3.3/5 V applications 4 Wide range of supply voltages 4 Input hysteresis 4 CMOS and TTL variants 4 Optional open-drain outputs, overvoltage-tolerant inputs Applications 4 Convert sine waves to square waves 4 Interface between analog and digital environments 4 Invoice noise immunity 4 Relaxation oscillators Schmitt triggers (cont.) Type number Description V CC (V) 74AHC132 74AHCT132 Quad 2-input NAND gate Schmitt trigger Quad 2-input NAND gate Schmitt trigger; TTL-enabled Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 2.0 to 5.5 CMOS ±8 3.3 50 pF 60 4 -40 to +125 4.5 to 5.5 TTL ±8 3.5 50 pF 60 4 -40 to +125 74AHC14 Hex inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 6 -40 to +125 74AHCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4 50 pF 60 6 -40 to +125 74AHC1G14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHCT1G14 Single inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125 74AHC3G14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125 74AHCT3G14 Triple inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125 74ALVC14 Hex inverter Schmitt trigger 1.65 to 3.6 TTL ±24 2.4 50 pF 150 6 -40 to +85 74AUP1G17 Single buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 1 -40 to +125 74AUP2G132 dual 2-input NAND gate Schmitt trigger 1.1 to 3.6 CMOS ±1.9 10 30 pF 70 2 -40 to +125 74AUP2G14 dual inverter Schmitt trigger 1.1 to 3.6 CMOS ±1.9 4.7 30 pF 70 2 -40 to +125 74AUP2G17 dual buffer Schmitt trigger 1.1 to 3.6 CMOS ±1.9 7.8 30 pF 70 2 -40 to +125 74HC132 74HCT132 Quad 2-input NAND gate Schmitt trigger Quad 2-input NAND gate Schmitt trigger; TTL-enabled 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125 4.5 to 5.5 TTL ±4 17 50 pF 36 4 -40 to +125 74HC14 Hex inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 6 -40 to +125 74HCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4 17 50 pF 36 6 -40 to +125 74HC1G14 Single inverter Schmitt trigger 2.0 to 6.0 CMOS ±2.6 10 50 pF 36 1 -40 to +125 74HCT1G14 Single inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±2.0 15 50 pF 36 1 -40 to +125 74HC2G14 Dual inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 2 -40 to +125 74HCT2G14 Dual inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125 74HC2G17 Dual buffer Schmitt trigger 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 2 -40 to +125 74HCT2G17 Dual buffer Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±4.0 21 50 pF 36 2 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 100 NXP Logic selection guide 2016
Schmitt triggers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 74HC3G14 Triple inverter Schmitt trigger 2.0 to 6.0 CMOS ±5.2 16 50 pF 36 3 -40 to +125 74HCT3G14 74HC7540 74HCT7540 74HC7541 74HCT7541 74HC9114 74HCT9114 74HC9115 74HCT9115 Triple inverter Schmitt trigger; TTL-enabled Octal inverter/line driver Schmitt trigger (3-state) Octal inverter/line driver Schmitt trigger; TTL-enabled (3-state) Octal buffer/line driver Schmitt trigger (3-state) Octal buffer/line driver Schmitt trigger; TTL-enabled (3-state) 9-bit inverter Schmitt trigger; open drain (3-state) 9-bit inverter Schmitt trigger; open drain; TTL-enabled (3-state) 9-bit buffer Schmitt trigger; open drain (3-state) 9-bit buffer Schmitt trigger; open drain; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4.0 21 50 pF 36 3 -40 to +125 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125 2.0 to 6.0 CMOS ±7.8 11 50 pF 36 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 36 8 -40 to +125 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125 2.0 to 6.0 CMOS 5,2 12 50 pF 36 9 -40 to +125 4.5 to 5.5 TTL 4 13 50 pF 36 9 -40 to +125 74HC7014 Hex buffer precision Schmitt trigger 2.0 to 6.0 CMOS ±5.2 27 50 pF 36 6 -40 to +125 74LV132 Quad 2-input NAND gate Schmitt trigger 1.0 to 5.5 TTL ±12 10 50 pF 30 4 -40 to +125 74LV14 Hex inverter Schmitt trigger 1.0 to 5.5 TTL ±12 13 50 pF 30 6 -40 to +125 74LVC132 Quad 2-input NAND gate Schmitt trigger 1.2 to 3.6 74LVC14 Hex inverter Schmitt trigger 1.2 to 3.6 74LVC1G14 Single inverter Schmitt trigger 1.65 to 5.5 74LVC1G17 Single buffer Schmitt trigger 1.65 to 5.5 74LVC2G14 Dual inverter Schmitt trigger 1.65 to 5.5 74LVC2G17 Dual buffer Schmitt trigger 1.65 to 5.5 74LVC3G14 Triple inverter Schmitt trigger 1.65 to 5.5 74LVC3G17 Triple buffer Schmitt trigger 1.65 to 5.5 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±24 3.4 50 pF 175 4 -40 to +125 ±24 3.2 50 pF 175 6 -40 to +125 ±32 3 50 pF 175 1 -40 to +125 ±32 3 50 pF 175 1 -40 to +125 ±32 3.9 50 pF 175 2 -40 to +125 ±32 3.6 50 pF 175 2 -40 to +125 ±32 3.2 50 pF 175 3 -40 to +125 ±32 3.6 50 pF 175 3 -40 to +125 74LVT14 Hex inverter Schmitt trigger 2.7 to 3.6 TTL -32 / +64 3.8 50 pF 150 6 -40 to +125 74VHCT14 Hex inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 6 -40 to +125 HEF40106 Hex inverter Schmitt trigger 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 6 -40 to +85 HEF4093 XC7SET14 Quad 2-input NAND gate Schmitt trigger Single inverter Schmitt trigger; TTL-enabled 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +125 4.5 to 5.5 TTL ±8 4.1 50 pF 60 1 -40 to +125 XC7SH14 Single inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 XC7WH14 Triple inverter Schmitt trigger 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 3 -40 to +125 XC7WT14 Triple inverter Schmitt trigger; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 60 3 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 101
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
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XC7 LOGIC XC7 devices are very high
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CBT(D) LOGIC CBT and CBTD bus switc
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LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99: PARITY GENERATORS/CHECKERS Features
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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