Logic selection guide 2016

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TRANSCEIVERS Features and benefits 4 Bidirectional operation 4 Mixed 3.3/5 V applications 4 Widths from 4 to 32 bits 4 Improve the current drive and signal levels 4 Improve signal integrity in complex layouts 4 Wide range of supply voltages 4 Low propagation delay 4 Registered options 4 Optional TTL inputs, source-termination resistors, overvoltage-tolerant inputs, bus hold Applications 4 Parallel backplanes 4 Telecommunications infrastructure 4 Industrial control 4 Test systems Transceivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability t pd (ns) Number of bits f max (MHz) Output Load C L (Typ) 74AHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS ±8 3.5 8 60 50 pF 74AHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 5 8 60 50 pF 74ALVC16245 16-bit transceiver (3-state) 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF 74ALVCH16245 16-bit transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 1.9 16 150 50 pF 74ALVC245 Octal transceiver (3-state) 1.65 to 3.6 TTL ±24 2.3 8 130 50 pF 74ALVCH162245 74ALVCH162601 74ALVCH16500 74ALVCH16501 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 18-bit universal bus transceiver with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 1.65 to 3.6 TTL ±12 2.4 16 150 50 pF 1.65 to 3.6 TTL ±12 3.1 18 150 50 pF 1.65 to 3.6 TTL ±24 2.9 18 150 50 pF 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 74ALVCH16543 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.8 16 150 50 pF 74ALVCH16600 74ALVCH16601 18-bit universal bus transceiver with bus hold; negative edge trigger (3-state) 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 1.65 to 3.6 TTL ±24 2.8 18 150 50 pF 74ALVCH16646 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 2.6 16 150 50 pF 74ALVCH16952 16-bit registered transceiver with bus hold (3-state) 1.65 to 3.6 TTL ±24 3.2 16 150 50 pF 74ALVT162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 2.3 to 3.6 TTL ±12 2.3 16 75 50 pF 74ALVT16245 16-bit transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.5 16 200 50 pF 74ALVT16501 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 2.3 to 3.6 TTL -32 / +64 1.8 18 150 50 pF 74ALVT16543 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 1.8 16 200 50 pF 74ALVT16601 18-bit universal bus transceiver with bus hold; positive edge trigger (3-state) 2.3 to 3.6 TTL -32 / +64 1.9 18 200 50 pF 74ALVT16652 16-bit registered transceiver with bus hold (3-state) 2.3 to 3.6 TTL -32 / +64 2.4 16 150 50 pF Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 104 NXP Logic selection guide 2016
Transceivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability t pd (ns) Number of bits f max (MHz) Output Load C L (Typ) 74AVC16245 16-bit transceiver (3-state) 1.2 to 3.6 CMOS ±12 2 16 200 30 pF 74AVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 CMOS ±12 2 16 200 30 pF 74HC245 Octal transceiver (3-state) 2.0 to 6.0 CMOS ±7.8 7 8 36 50 pF 74HCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 10 8 36 50 pF 74HC640 Octal transceiver; inverting (3-state) 2.0 to 6.0 CMOS ±7.8 9 8 36 50 pF 74HCT640 Octal transceiver; inverting; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 9 8 36 50 pF 74HC652 Octal registered transceiver (3-state) 2.0 to 6.0 CMOS ±7.8 13 8 36 50 pF 74HCT652 Octal registered transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 13 8 36 50 pF 74LV245 Octal transceiver (3-state) 1.0 to 5.5 TTL ±16 7 8 30 50 pF 74LVC162245 16-bit transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 16 175 50 pF 74LVCH162245 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 16 175 50 pF 74LVC16245 16-bit transceiver (3-state) 1.2 to 3.6 74LVCH16245 16-bit transceiver with bus hold (3-state) 1.2 to 3.6 74LVC245 Octal transceiver (3-state) 1.2 to 3.6 74LVCH245 Octal transceiver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±24 3 16 175 50 pF ±24 3 16 175 50 pF ±24 2.9 8 175 50 pF ±24 2.9 8 175 50 pF 74LVC2245 Octal transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 8 175 50 pF 74LVC2952 Octal registered transceiver with 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 4.3 8 175 50 pF 74LVC32245 32-bit transceiver (3-state) 1.2 to 3.6 74LVC543 Octal registered transceiver (3-state) 1.2 to 3.6 74LVC544 Octal registered transceiver; inverting (3-state) 1.2 to 3.6 74LVC623 Octal transceiver with dual enable (3-state) 1.2 to 3.6 74LVC646 Octal registered transceiver (3-state) 1.2 to 3.6 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±24 2.2 32 175 50 pF ±24 3.3 8 175 50 pF ±24 4 8 175 50 pF ±24 3.3 8 175 50 pF ±24 3.9 8 175 50 pF 74LVCH322245 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 CMOS/ LVTTL ±12 3.3 32 175 50 pF 74LVCH32245 32-bit transceiver with bus hold (3-state) 1.2 to 3.6 CMOS/ LVTTL ±24 3 32 175 50 pF 74LVT16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVTH16245 16-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT2245 Octal transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 3.2 8 150 50 pF Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 105
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
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XC7 LOGIC XC7 devices are very high
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CBT(D) LOGIC CBT and CBTD bus switc
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LV selection table TSSOP SSOP SO DQ
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LVC selection table (cont.) TSSOP V
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LVC selection table (cont.) TSSOP V
Page 53 and 54: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103: Shift registers - LED drivers (cont
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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