Logic selection guide 2016

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Flip-flops (cont.) Type number Description V CC (V) 74LVT574 74LVTH57 74LVTH574 74LVT162374 74LVT273 74LVT32374 Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) Octal D-type flip-flop with reset; positive-edge trigger 32-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 2.7 to 3.6 TTL -32/+64 4,3 50 pF 150 -40 to +85 2.7 to 3.6 TTL ±12 3 50 pF 150 -40 to +85 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 74LVT373 Octal D-type transparent latch (3-state) 2.7 to 3.6 TTL -32/+64 3 50 pF -40 to +85 74LVT374 74LVT534 74LVT74 HEF4013 HEF40174 HEF40175 Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; inverting; positive-edge trigger (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger Dual D-type flip-flop with set and reset; positiveedge trigger Hex D-type flip-flop with reset; positive-edge trigger Quad D-type flip-flop with reset; positive-edge trigger 2.7 to 3.6 TTL -32/+64 3,5 50 pF 200 -40 to +85 2.7 to 3.6 TTL -32/+64 3,5 50 pF 150 -40 to +85 2.7 to 3.6 TTL -20/+32 3,6 50 pF 345 -40 to +85 4.5 to 15.5 CMOS ±2.4 30 50 pF 40 -40 to +85 4.5 to 15.5 CMOS ±2.4 20 50 pF 45 -40 to +85 4.5 to 15.5 CMOS ±2.4 25 50 pF 45 -40 to +85 HEF4027 Dual JK-type flip-flop 4.5 to 15.5 CMOS ±2.4 30 50 pF 30 -40 to +85 HEF40374 Octal D-type flip-flop; positive-edge trigger (3-state) 4.5 to 15.5 CMOS -50/+62 40 50 pF 17 -40 to +85 FULL ADDERS Features and benefits 4 Cascadable 4 Low power dissipation 4 Positive or negative logic 4 Wide range of supply voltages Applications 4 High-speed 4-bit binary addition Full adders Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output drive capability (mA) Number of bits T amb (°C) 74HC283 4-bit binary full adder with fast carry 2.0 to 6.0 CMOS ±5.2 21 50 pF 4 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 86 NXP Logic selection guide 2016
GATES This section includes AND gates, combination gates (one package, two or more different functions), configurable multi-function gates (one package, nine or more functions), EXCLUSIVE-NOR gates, EXCLUSIVE-OR gates, NOR gates, and OR gates. Features and benefits 4 Mixed 3.3/5 V applications 4 Reduced time-to-market for complex designs 4 Reduced board space 4 Improved signal integrity in complex layouts 4 Wide range of supply voltages 4 Low propagation delay 4 Low-power CMOS 4 Optional overvoltage-tolerant inputs, low input threshold 4 Comprehensive range: AND, EXCLUSIVE-NOR, EXCLUSIVE-OR, NAND, NOR, OR 4 Combination gates and configurable multi-function gates for lower pincount, device count, system cost, assemblyrelated expenses Applications 4 Control/glue logic 4 PCB miniaturization 4 Routing simplification 4 Discrete replacement Gates - AND (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 74AHC08 Quad 2-input AND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 4 -40 to +125 74AHC1G08 Single 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHC1G09 Single 2-input AND gate; open drain 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 -40 to +125 74AHC2G08 Dual 2-input AND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 2 -40 to +125 74AHCT08 74AHCT1G08 74AHCT2G08 Quad 2-input AND gate; TTL-enabled Single 2-input AND gate; TTL-enabled Dual 2-Input AND gate; TTL-enabled 4.5 to 5.5 TTL ±8 5 50 pF 60 4 -40 to +125 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125 74ALVC08 Quad 2-input AND gate 1.65 to 3.6 TTL ±24 2 50 pF 145 4 -40 to +85 74AUP1G08 Single 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 1 -40 to +125 74AUP1G09 Single 2-input AND gate; open drain 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125 74AUP1G11 Single 3-input AND gate 1.1 to 3.6 CMOS ±1.9 6.9 30 pF 70 1 -40 to +125 74AUP2G08 Dual 2-input AND gate 1.1 to 3.6 CMOS ±1.9 8.2 30 pF 70 2 -40 to +125 74AXP1G08 Single 2-input AND gate 0.7 to 2.75 CMOS ±4.5 2.6 5pF 70 1 -40 to +85 74HC08 Quad 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125 74HC11 Triple 3-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 3 -40 to +125 74HC1G08 Single 2-input AND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 1 -40 to +125 74HC21 Dual 4-input AND gate 2.0 to 6.0 CMOS ±5.2 10 50 pF 36 2 -40 to +125 74HC2G08 Dual 2-input AND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74HCT08 Quad 2-input AND gate; TTL-enabled 4.5 to 5.5 TTL ±4 11 50 pF 36 4 -40 to +125 74HCT11 Triple 3-input AND gate 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125 74HCT1G08 74HCT1G08 Single 2-input AND gate; TTL-enabled Single 2-input AND gate; TTL-enabled 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125 4.5 to 5.5 TTL ±2 11 50 pF 36 1 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 87
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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Page 35 and 36: HC(T) selection table (cont.) TSSOP
Page 37 and 38: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85: Flip-flops (cont.) Type number Desc
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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