Logic selection guide 2016

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ANALOG SWITCHES Features and benefits 4 Reduced signal attenuation for low switching losses 4 Reduced THD for high-quality audio switching 4 Fewer ADCs with analog sensor multiplexing 4 Integrated level shifting 4 Low ON resistance, ON flatness 4 Low switch leakage 4 Wide supply voltage 4 Options for low input threshold 4 Overvoltage-tolerant options 4 High ESD protection per IEC 61000 standard Applications 4 Audio/video source selection 4 Analog sensor multiplexing 4 GPIO expansion 4 Bus isolation 4 Sample-and-hold circuits Analog switches (cont.) Type number 74AHC1G66 74AHCT1G66 74HC1G66 74HCT1G66 74HC2G66 74HCT2G66 74HC4016 74HCT4016 74HC4051 74HCT4051 74HC4052 74HCT4052 74HC4053 74HCT4053 74HC4066 74HCT4066 74HC4067 74HCT4067 74HC4316 Description Single-pole, single-throw analog switch Single-pole, single-throw analog switch; TTL-enabled Single-pole, single-throw analog switch Single-pole, single-throw analog switch; TTL-enabled Dual single-pole, single-throw analog switch Dual single-pole, single-throw analog switch; TTL-enabled Quad single-pole, single-throw analog switch Quad single-pole, single-throw analog switch; TTL-enabled Single-pole, octal-throw analog switch Single-pole, octal-throw analog switch; TTL-enabled Dual single-pole, quad-throw analog switch Dual single-pole, quad-throw analog switch; TTL-enabled Triple single-pole, double-throw analog switch Triple single-pole, double-throw analog switch; TTL-enabled Quad single-pole, single-throw analog switch Quad single-pole, single-throw analog switch; TTL-enabled Single-pole, 16-throw analog switch Single-pole, 16-throw analog switch; TTL-enabled Quad single-pole, single-throw analog switch with translation V CC (V) Logic switching levels R ON (Ω) R ON (FLAT) (Ω) f(-3dB) (MHz) T HD (%) X talk (dB) T amb (°C) 2.0 to 5.5 CMOS 40 14 280 0.015 -40 to +125 4.5 to 5.5 TTL 40 14 280 0.015 -40 to +125 2.0 to 9.0 CMOS 105 23 200 0.02 -40 to +125 4.5 to 5.5 TTL 118 23 180 0.04 -40 to +125 2.0 to 9.0 CMOS 105 23 200 0.02 -60 -40 to +125 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125 2.0 to 10.0 CMOS 300 80 160 0.4 -60 -40 to +125 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125 2.0 to 10.0 CMOS 200 20 180 0.02 -60 -40 to +125 4.5 to 5.5 TTL 225 20 170 0.04 -60 -40 to +125 2.0 to 10.0 CMOS 200 20 170 0.02 -40 to +125 4.5 to 5.5 TTL 225 20 160 0.04 -40 to +125 2.0 to 10.0 CMOS 105 23 200 0.02 -60 -40 to +125 4.5 to 5.5 TTL 118 23 180 0.04 -60 -40 to +125 2.0 to 10.0 CMOS 200 25 100 0.02 -40 to +125 4.5 to 5.5 TTL 225 25 90 0.04 -40 to +125 2.0 to 10.0 CMOS 300 80 160 0.4 -60 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 66 NXP Logic selection guide 2016
Analog switches (cont.) Type number 74HCT4316 74HC4351 74HCT4351 74HC4353 74HCT4353 74HC4851 74HCT4851 74HC4852 74HCT4852 74LV4051 74LV4052 74LV4053 74LV4066 74LVC1G3157 74LVC1G384 74LVC1G53 74LVC1G66 74LVC2G53 74LVC2G66 74LVC4066 74LVCV2G66 HEF4016 HEF4051 HEF4052 HEF4053 HEC4066 HEF4067 Description Quad single-pole, single-throw analog switch with translation; TTL-enabled Single-pole, octal-throw analog switch with latch Single-pole, octal-throw analog switch with latch; TTL-enabled Triple single-pole, double-throw analog switch with latch Triple single-pole, double-throw analog switch with latch; TTL-enabled Single-pole, octal-throw analog switch Single-pole, octal-throw analog switch; TTL-enabled Dual single-pole, quad-throw analog switch; TTL-enabled Dual single-pole, quad-throw analog switch; TTL-enabled Single-pole, octal-throw analog switch Dual single-pole, quad-throw analog switch Triple single-pole, double-throw analog switch Quad single-pole, single-throw analog switch Single-pole, double-throw analog switch Single-pole, single-throw analog switch Single-pole, double-throw analog switch Single-pole, single-throw analog switch Single-pole, double-throw analog switch Dual single-pole, single-throw analog switch Quad single-pole, single-throw analog switch Dual single-pole, single-throw analog switch; overvoltage tolerant Quad single-pole, single-throw analog switch Single-pole, octal-throw analog switch Dual single-pole, quad-throw analog switch Triple single-pole, double-throw analog switch Quad single-pole, single-throw analog switch Single-pole, 16-throw analog switch V CC (V) Logic switching levels R ON (Ω) R ON (FLAT) (Ω) f(-3dB) (MHz) T HD (%) X talk (dB) T amb (°C) 4.5 to 5.5 TTL 400 50 150 0.8 -60 -40 to +125 2.0 to 10.0 CMOS 200 20 180 0.02 -40 to +125 4.5 to 5.5 TTL 225 20 170 0.04 -40 to +125 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125 4.5 to 5.5 TTL 225 20 160 0.04 -60 -40 to +125 2.0 to 10.0 CMOS 220 -40 to +125 4.5 to 5.5 TTL 240 -40 to +125 2.0 to 10.0 CMOS 220 -40 to +125 4.5 to 5.5 TTL 240 -40 to +125 1.0 to 6.0 TTL 135 35 200 0.4 -60 -40 to +125 1.0 to 6.0 TTL 125 15 180 0.4 -60 -40 to +125 1.0 to 6.0 TTL 150 30 180 0.4 -60 -40 to +125 1.0 to 6.0 TTL 50 3 180 0.02 -60 -40 to +125 1.65 to 5.5 1.65 to 5.5 1.65 to 5.5 1.65 to 5.5 1.65 to 5.5 1.65 to 5.5 1.65 to 5.5 2.3 to 5.5 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL 15 1,5 300 0.078 -40 to +125 15 1,5 440 0.001 -40 to +125 15 1,5 300 0.078 -40 to +125 15 1,5 440 0.001 -40 to +125 15 1,5 300 0.078 -40 to +125 15 1,5 440 0.005 -40 to +125 15 1,5 440 0.005 -40 to +125 15 3 210 0.01 -40 to +125 4.5 to 15.5 CMOS 350 65 90 0.04 -50 -40 to +85 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 4.5 to 15.5 CMOS 175 30 70 0.04 -50 -40 to +85 4.5 to 15.5 CMOS 175 20 90 0.04 -50 -40 to +85 4.5 to 15.5 CMOS 175 20 13 0.04 -50 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 67
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65: Product listing by function Analog
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
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Level shifters/translators Features
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Shift registers (cont.) Features Pa
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Standard logic packages Package suf
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Buffers/inverters (cont.) Features
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Digital decoders/demultiplexers Fea
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Gates (cont.) Features Package (suf
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Level shifters/translators Features
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The leadless advantage Today’s ul
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Nomenclature NXP's naming conventio
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SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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