Logic selection guide 2016

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HC(T) LOGIC HC(T) devices are high-speed CMOS logic available in the industry’s broadest range of functions. HC products are for use in CMOS applications from 2.0 to 6.0 V and HCT products are for use in TTL applications from 4.5 to 5.5 V. All HC(T) devices offer a balanced output drive of 8 mA and a typical propagation delay of 9 ns, and are fully specified from -40 to +125 °C. Features and benefits 4 9 ns typical propagation delay 4 Output drive capability I OH / I OL = ±8 mA 4 Low power 4 Input clamp diodes 4 Broad portfolio Applications 4 Industrial 4 Consumer electronics 4 Computer peripherals HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Type number Function Description Suffix DP, PW 74HC00 NAND gates quad 2-input NAND gate • • • • 74HCT00 NAND gates quad 2-input NAND gate; TTL-enabled Suffix DC Suffix DB Suffix D Suffix BQ • • • • 74HC02 NOR gates quad 2-input NOR gate • • • • 74HCT02 NOR gates quad 2-input NOR gate; TTL-enabled • • • • 74HC03 NAND gates quad 2-input NAND gate; open-drain • • • 74HCT03 74HC04 74HCT04 NAND gates Buffers/inverters/ drivers Buffers/inverters/ drivers quad 2-input NAND gate; open-drain; TTL-enabled • • • hex inverter • • • • hex inverter; TTL-enabled • • • • 74HC08 AND gates quad 2-input AND gate • • • • 74HCT08 AND gates quad 2-input AND gate; TTL-enabled • • • • 74HC10 NAND gates triple 3-input NAND gate • • • 74HCT10 74HC107 74HCT107 74HC109 74HCT109 NAND gates J-K type flip-flops J-K type flip-flops J-K type flip-flops J-K type flip-flops triple 3-input NAND gate; TTL-enabled dual J-K flip-flop with reset; negativeedge trigger dual J-K flip-flop with reset; negativeedge trigger; TTL-enabled dual J-/K flip-flop with set and reset; positive-edge trigger dual J-/K flip-flop with set and reset; positive-edge trigger; TTL-enabled • • • • • • • • • • • 74HC11 AND gates triple 3-input AND gate • • • 74HCT11 AND gates triple 3-input AND gate; TTL-enabled • • • • Suffix GD, GM, GT Suffix GW, GV 74HC112 74HCT112 74HC123 74HCT123 74HC125 J-K type flip-flops J-K type flip-flops Multivibrators Multivibrators Buffers/inverters/ drivers dual J-K flip-flop with set and reset; negative-edge trigger dual J-K flip-flop with set and reset; negative-edge trigger; TTL-enabled dual retriggerable monostable multivibrator with reset dual retriggerable monostable multivibrator with reset; TTL-enabled • • • • • • • • • • • • • • quad buffer/line driver (3-state) • • • • 28 NXP Logic selection guide 2016
HC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Type number 74HCT125 74HC126 74HCT126 74HC132 74HCT132 74HC138 74HCT138 74HC139 74HCT139 Function Buffers/inverters/ drivers Buffers/inverters/ drivers Buffers/inverters/ drivers Schmitt triggers Schmitt triggers Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers Decoders/ demultiplexers Description quad buffer/line driver (3-state); TTL-enabled Suffix DP, PW Suffix DC Suffix DB Suffix D • • • quad buffer/line driver (3-state) • • • quad buffer/line driver (3-state); TTL-enabled quad 2-input NAND gate Schmitt trigger quad 2-input NAND gate Schmitt trigger; TTL-enabled 3-to-8 line decoder/demultiplexer; inverting 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled • • • • • • • • • Suffix BQ • • • • • • • • dual 2-to-4 line decoder/demultiplexer • • • • dual 2-to-4 line decoder/ demultiplexer; TTL-enabled • • • • 74HC14 Schmitt triggers hex inverter Schmitt trigger • • • • 74HCT14 Schmitt triggers hex inverter Schmitt trigger; TTL-enabled • • • • 74HC147 Encoders 10-to-4 line priority encoder • • 74HCT147 Encoders 10-to-4 line priority encoder; TTL-enabled 74HC151 Digital multiplexers 8-input multiplexer • • • 74HCT151 Digital multiplexers 8-input multiplexer; TTL-enabled • • • 74HC153 Digital multiplexers dual 4-input multiplexer • • • 74HCT153 Digital multiplexers dual 4-input multiplexer; TTL-enabled • • • 74HC154 74HCT154 Decoders/ demultiplexers Decoders/ demultiplexers • 4-to-16 line decoder/demultiplexer • • • • 4-to-16 line decoder/demultiplexer; TTL-enabled • • • • 74HC157 Digital multiplexers quad 2-input multiplexer • • • • 74HCT157 Digital multiplexers quad 2-input multiplexer; TTL-enabled • • • • 74HC160 74HCT160 74HC161 74HCT161 74HC163 74HCT163 BCD/decade counters BCD/decade counters Binary counters/ timers Binary counters/ timers Binary counters/ timers Binary counters/ timers presettable synchronous BCD decade counter; asynchronous reset presettable synchronous BCD decade counter; asynchronous reset; TTL-enabled presettable synchronous 4-bit binary counter; asynchronous reset presettable synchronous 4-bit binary counter; asynchronous reset; TTL-enabled presettable synchronous 4-bit binary counter; synchronous reset presettable synchronous 4-bit binary counter; synchronous reset; TTL-enabled • • • • • • • • • • • • • • • • • 74HC164 Shift registers 8-bit serial-in/parallel-out shift register • • • • 74HCT164 74HC165 74HCT165 Shift registers Shift registers Shift registers 8-bit serial-in/parallel-out shift register; TTL-enabled 8-bit parallel or serial-in/serial-out shift register 8-bit parallel or serial-in/serial-out shift register; TTL-enabled • • • • • • • • • • • • Suffix GD, GM, GT Suffix GW, GV NXP Logic selection guide 2016 29
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27: HEF4000B selection table (cont.) SO
Page 31 and 32: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80:
Decoders demultiplexers (cont.) Typ
Page 81 and 82:
Digital multiplexers (cont.) Type n
Page 83 and 84:
Flip-flops (cont.) Type number Desc
Page 85 and 86:
Flip-flops (cont.) Type number Desc
Page 87 and 88:
GATES This section includes AND gat
Page 89 and 90:
Gates - Configurable Type number De
Page 91 and 92:
Gates - NAND (cont.) Type number De
Page 93 and 94:
Gates - OR (cont.) Type number Desc
Page 95 and 96:
Latches-registered drivers (cont.)
Page 97 and 98:
Level shifters-translators (cont.)
Page 99 and 100:
PARITY GENERATORS/CHECKERS Features
Page 101 and 102:
Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138:
SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140:
SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144:
SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146:
SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148:
SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
Page 153 and 154:
Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
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