Logic selection guide 2016

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AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Type number Function Description 74AHCT1G86 74AHC240 74AHCT240 74AHC244 74AHCT244 EXCLUSIVE- OR gate Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver 2-input EXCLUSIVE-OR gate TTL-enabled Octal inverter/line driver (3-state) Octal inverter/line driver; TTLenabled (3-state) Suffix PW Suffix DC Suffix DB Suffix D Suffix BQ • • • Octal buffer/line driver (3-state) • • • Octal buffer/line driver; TTL-enabled (3-state) • • • 74AHC245 Transceiver Octal transceiver (3-state) • • • 74AHCT245 74AHC257 74AHCT257 74AHC259 74AHCT259 74AHC273 74AHCT273 Transceiver Digital multiplexer Digital multiplexer Latch/ registered driver Latch/ registered driver D-type flip-flop D-type flip-flop Octal transceiver; TTL-enabled (3-state) • • • Quad 2-input multiplexer (3-state) • • Quad 2-input multiplexer; TTL-enabled (3-state) • • 8 bit addressable latch • • 8-Bit addressable latch; TTL-enabled • • Octal D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled • • • • • • • Suffix GD, GF, GM, GN, GS, GT 74AHC2G00 NAND gate Dual 2-input NAND gate • • • 74AHCT2G00 NAND gate Dual 2-input NAND gate; TTL-enabled Suffix DP, GW, GV • • • 74AHC2G08 AND gate Dual 2-input AND gate • • • 74AHCT2G08 AND gate Dual 2-Input AND gate; TTL-enabled • • • 74AHC2G125 74AHCT2G125 74AHC2G126 74AHCT2G126 74AHC2G241 74AHCT2G241 Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Dual buffer/line driver (3-state) • • • Dual buffer/line driver; TTL-enabled (3-state) • • • Dual buffer/line driver (3-state) • • • Dual buffer/line driver; TTL-enabled (3-state) • • • Dual buffer/line driver (3-state) • • • Dual buffer/line driver; TTL-enabled (3-state) • • • 74AHC2G32 OR gate Dual 2-input OR gate • • • 74AHCT2G32 OR gate Dual 2-input OR gate • • • 74AHC30 NAND gate 8-input NAND gate • • • 74AHCT30 NAND gate 8-input NAND gate; TTL-enabled • • • 74AHC32 OR gate Quad 2-input OR gate • • • 74AHCT32 OR gate Quad 2-input OR gate; TTL-enabled • • • 74AHC373 74AHCT373 Latch/ registered driver Latch/ registered driver Octal D-type transparent latch (3-state) Octal D-type transparent latch; TTL-enabled (3-state) • • • • • 40 NXP Logic selection guide 2016
AHC(T) selection table (cont.) TSSOP VSSOP SSOP SO DQFN MicroPak PicoGate Type number Function Description 74AHC374 74AHCT374 74AHC377 74AHCT377 74AHC3G04 74AHCT3G04 D-type flip-flop D-type flip-flop D-type flip-flop D-type flip-flop Buffer/inverter/ driver Buffer/inverter/ driver Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop with data enable; positive-edge trigger Octal D-type flip-flop with data enable; positive-edge trigger; TTL-enabled Suffix PW Suffix DC Suffix DB Suffix D • • • • • • • • Suffix BQ Suffix GD, GF, GM, GN, GS, GT Suffix DP, GW, GV Triple inverter • • • Triple inverter; TTL-enabled • • • 74AHC3G14 Schmitt trigger Triple inverter Schmitt trigger • • • 74AHCT3G14 74AHC541 74AHCT541 74AHC573 74AHCT573 74AHC574 74AHCT574 74AHC594 74AHCT594 74AHC595 74AHCT595 74AHC74 74AHCT74 74AHC86 74AHCT86 Schmitt trigger Buffer/inverter/ driver Buffer/inverter/ driver Latch/ registered driver Latch/ registered driver D-type flip-flop D-type flip-flop Shift register Shift register Shift register Shift register D-type flip-flop D-type flip-flop EXCLUSIVE- OR gate EXCLUSIVE- OR gate Triple inverter Schmitt trigger; TTL-enabled • • • Octal buffer/line driver (3-state) • • • Octal buffer/line driver; TTL-enabled (3-state) Octal D-type transparent latch (3-state) Octal D-type transparent latch; TTL-enabled (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) 8-bit serial-in/parallel-out shift register with output storage register 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled 8-bit serial-in/parallel-out shift register with output storage register (3-state) 8-bit serial-in/parallel-out shift register with output storage register; TTL-enabled (3-state) Dual D-type flip-flop with set and reset; positive-edge trigger Dual D-type flip-flop with set and reset; positive-edge trigger; TTL-enabled • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Quad 2-input EXCLUSIVE-OR gate • • • Quad 2-input EXCLUSIVE-OR gate; TTL-enabled • • • 74AHC1G09 AND gate Single 2-input AND gate; open drain • 74AHC1GU04 74AHC3GU04 74AHCU04 Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Single inverter; unbuffered Triple inverter; unbuffered • • • Hex inverter; unbuffered • • • • NXP Logic selection guide 2016 41
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92:
Gates - NAND (cont.) Type number De
Page 93 and 94:
Gates - OR (cont.) Type number Desc
Page 95 and 96:
Latches-registered drivers (cont.)
Page 97 and 98:
Level shifters-translators (cont.)
Page 99 and 100:
PARITY GENERATORS/CHECKERS Features
Page 101 and 102:
Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138:
SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140:
SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142:
SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144:
SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146:
SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148:
SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150:
SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152:
Design tools NXP is committed to ma
Page 153 and 154:
Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
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