Logic selection guide 2016

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LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVC2G38 74LVC2G53 74LVC2G66 74LVC2G74 74LVC2G86 74LVC2GU04 NAND gate Analog switch Analog switch D-type flip-flop EXCLUSIVE-OR gate Buffer/inverter/ driver Dual 2-input NAND gate; open drain Single-pole, double-throw analog switch Dual single-pole, single-throw analog switch Single D-type flip-flop with set and reset; positive-edge trigger Dual 2-input EXCLUSIVE-OR gate Suffix DGG, PW Suffix DC Suffix DB, DL Suffix D Suffix BQ, BX Suffix EC, EV Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • • • • • • • • • • • • • • • • • • • Dual inverter; unbuffered • • • • 74LVC32245A Transceiver 32-bit transceiver (3-state) • 74LVC32A OR gate Quad 2-input OR gate • • • • 74LVC373A 74LVC374A 74LVC377 74LVC38A 74LVC3G04 74LVC3G06 74LVC3G07 Latch/registered driver D-type flip-flop D-type flip-flop NAND gate Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Octal D-type transparent latch (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop with data enable; positive-edge trigger Quad 2-input NAND gate; open drain • • • • • • • • • • • • • • • Triple inverter • • • Triple inverter; open drain • • • Triple buffer; open drain • • • 74LVC3G14 Schmitt trigger Triple inverter Schmitt trigger • • • 74LVC3G17 Schmitt trigger Triple buffer Schmitt trigger • • • 74LVC3G34 74LVC3GU04 74LVC4066 74LVC4245A 74LVC541A 74LVC543A 74LVC544A 74LVC573A 74LVC574A 74LVC594A Buffer/inverter/ driver Buffer/inverter/ driver Analog switch Level shifter/ translator Buffer/inverter/ driver Transceiver Transceiver Latch/registered driver D-type flip-flop Shift register Triple buffer • • • Triple inverter; unbuffered • • • Quad single-pole, singlethrow analog switch 8-bit dual-supply voltagetranslating transceiver (3-state) Octal buffer/line driver (3-state) Octal registered transceiver (3-state) Octal registered transceiver; inverting (3-state) Octal D-type transparent latch (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) 8-bit serial-in/parallel-out shift register with output storage register • • • • • • • • • • • • • • • • • • • • • • • • • • • 52 NXP Logic selection guide 2016
LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVC595A 74LVC623A 74LVC646A 74LVC74A 74LVC821A 74LVC827A 74LVC841A 74LVC86A 74LVCH162374A 74LVCH16541A 74LVCH322244A 74LVCH322245A 74LVCH32244A 74LVCH32245A 74LVCH32373A 74LVCH32374A 74LVCU04A 74LVCV2G66 Shift register Transceiver Transceiver D-type flip-flop D-type flip-flop Buffer/inverter/ driver Latch/registered driver EXCLUSIVE-OR gate D-type flip-flop Buffer/inverter/ driver Buffer/inverter/ driver Transceiver Buffer/inverter/ driver Transceiver Latch/registered driver D-type flip-flop Buffer/inverter/ driver Analog switch 8-bit serial-in/parallel-out shift register with output storage register (3-state) Octal transceiver with dual enable (3-state) Octal registered transceiver (3-state) Dual D-type flip-flop with set and reset; positive-edge trigger 10-bit D-type flip-flop; positive-edge trigger (3-state) 10-bit buffer/line driver (3-state) 10-bit D-type transparent latch (3-state) Quad 2-input EXCLUSIVE-OR gate 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positiveedge trigger (3-state) 16-bit buffer/line driver with bus hold (3-state) 32-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 32-bit buffer/line driver with bus hold (3-state) 32-bit transceiver with bus hold (3-state) 32-bit D-type transparent latch (3-state) 32-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) Suffix DGG, PW Suffix DC Suffix DB, DL Suffix D Suffix BQ, BX • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Hex inverter; unbuffered • • Dual single-pole, single-throw analog switch; overvoltage tolerant Suffix EC, EV • • • • • • Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • NXP Logic selection guide 2016 53
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 51: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138:
SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140:
SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142:
SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144:
SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146:
SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148:
SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150:
SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152:
Design tools NXP is committed to ma
Page 153 and 154:
Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
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