Logic selection guide 2016

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Buffers/inverters (cont.) Features Package (suffix) Type number Description 74AHC04-Q100 Hex inverter 2.0 - 5.5 ± 8 3 -40~125 • • • 74AHCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ± 8 3 -40~125 • • • 74AHC125-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ± 8 3 -40~125 • • • 74AHCT125-Q100 Quad buffer/line driver; TTL-enabled (3-state) V CC (V) I O (mA) t pd (ns) T amb (°C) SOT108-1 (D) SOT337-1 (DB) SOT402-1 (PW) 4.5 - 5.5 ± 8 3 -40~125 • • • 74AHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.3 -40~125 • • • 74AHCT126-Q100 74AHC240-Q100 74AHCT240-Q100 Quad buffer/line driver; TTL-enabled (3-state) Octal inverter/line driver (3-state) Octal inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3 -40~125 • • • 2.0 - 5.5 ± 8 2.8 -40~125 • • • 4.5 - 5.5 ± 8 3 -40~125 • • • 74AHC244-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.5 -40~125 • • • 74AHCT244-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.5 -40~125 • • • 74AHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.5 -40~125 • • • 74AHCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.5 -40~125 • • • 74AHCU04-Q100 Hex inverter; unbuffered 2.0 - 5.5 ± 8 2.4 -40~125 • • • 74ALVC125-Q100 Quad buffer/line driver (3-state) 1.65 - 3.6 ± 24 1.8 -40~85 • • • 74ALVC541-Q100 Octal buffer/line driver (3-state) 1.65 - 3.6 ± 24 2.3 -40~85 • • • 74HC05-Q100 Hex inverter; open-drain 2.0 - 6.0 5.2 11 -40~125 • • • 74HC04-Q100 Hex inverter 2.0 - 6.0 ± 5.2 7 -40~125 • • • • 74HCT04-Q100 Hex inverter; TTL-enabled 4.5 - 5.5 ± 4.0 8 -40~125 • • • 74HC125-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • 74HCT125-Q100 Quad buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 6 12 -40~125 • • 74HC126-Q100 Quad buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • 74HCT126-Q100 74HC240-Q100 74HCT240-Q100 Quad buffer/line driver; TTL-enabled (3-state) Octal inverter/line driver (3-state) Octal inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 6 11 -40~125 • • 2.0 - 6.0 ± 7.8 9 -40~125 • • • 4.5 - 5.5 ± 6 9 -40~125 • • • 74HC244-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • • 74HCT244-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 6 11 -40~125 • • • 74HC365-Q100 Hex buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 9 -40~125 • • 74HCT365-Q100 Hex buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 6 11 -40~125 • • 74HC366-Q100 Hex inverter/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • • 74HCT366-Q100 Hex inverter/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 6 11 -40~125 • • SOT762-1 (BQ) SOT109-1 (D) SOT403-1 (PW) SOT163-1 (D) SOT339-1 (DB) SOT360-1 (PW) SOT764-1 (BQ) SOT362-1 (DGG) 108 NXP Logic selection guide 2016
Buffers/inverters (cont.) Features Package (suffix) Type number 74HC540-Q100 74HCT540-Q100 Description Octal inverter/line driver (3-state) Octal inverter/line driver; TTL-enabled (3-state) V CC (V) I O (mA) t pd (ns) T amb (°C) 2.0 - 6.0 ± 7.8 9 -40~125 • 4.5 - 5.5 ± 6 11 -40~125 • 74HC541-Q100 Octal buffer/line driver (3-state) 2.0 - 6.0 ± 7.8 10 -40~125 • • 74HCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) SOT108-1 (D) 4.5 - 5.5 ± 6 12 -40~125 • • 74HCU04-Q100 Hex inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 • • • 74LV244-Q100 Octal buffer/line driver (3-state) 1.0 - 5.5 ± 16 8 -40~125 • • 74LVC04A-Q100 Hex inverter 1.65 - 5.5 ± 24 2 -40~125 • • • 74LVC06A-Q100 Hex inverter; open-drain 1.65 - 5.5 32 2.2 -40~125 • • • 74LVC07A-Q100 Hex buffer; open-drain 1.65 - 5.5 32 2.2 -40~125 • • • 74LVC125A-Q100 Quad buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • • • 74LVC126A-Q100 Quad buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.4 -40~125 • • • 74LVC541A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 3.3 -40~125 • • • 74LVC16240A-Q100 16-bit inverter/line driver (3-state) SOT337-1 (DB) 1.2 - 3.6 ± 24 2.7 -40~125 • 74LVC244A-Q100 Octal buffer/line driver (3-state) 1.2 - 3.6 ± 24 2.8 -40~125 • • • • 74LVCH244A-Q100 Octal buffer/line driver with bus hold (3-state) 1.2 - 3.6 ± 24 2.8 -40~125 • • • 74LVC16244A-Q100 16-bit buffer/line driver (3-state) 1.2 - 3.6 ± 24 3 -40~125 • 74LVCH16244A-Q100 16-bit buffer/line driver with bus hold (3-state) 1.2 - 3.6 ± 24 3 -40~125 • 74LVT04-Q100 Hex inverter 2.7 - 3.6 -20 / +32 2.6 -40~85 • • • 74LVT244A-Q100 74LVTH244A-Q100 Octal buffer/line driver with bus hold (3-state) Octal buffer/line driver with bus hold (3-state) 2.7 - 3.6 -32 / +64 2.6 -40~85 • • 2.7 - 3.6 -32 / +64 2.6 -40~85 • • 74VHC126-Q100 Quad buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.3 -40~125 • • • 74VHCT126-Q100 Quad buffer/line driver; TTL-enabled (3-state) SOT402-1 (PW) 4.5 - 5.5 ± 8 3 -40~125 • • • 74VHC541-Q100 Octal buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.5 -40~125 • • • 74VHCT541-Q100 Octal buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.5 -40~125 • • • HEF4049B-Q100 Hex inverter/line driver 3.0 - 15.0 -3 / +20 20 -40~85 • HEF4050B-Q100 Hex buffer/line driver 3.0 - 15.0 -3 / +20 40 -40~85 • HEF4069UB-Q100 Hex inverter; unbuffered 3.0 - 15.0 ± 3.4 15 -40~85 • • SOT762-1 (BQ) SOT109-1 (D) SOT403-1 (PW) SOT163-1 (D) SOT339-1 (DB) SOT360-1 (PW) SOT764-1 (BQ) SOT362-1 (DGG) NXP Logic selection guide 2016 109
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
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XC7 LOGIC XC7 devices are very high
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CBT(D) LOGIC CBT and CBTD bus switc
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LV selection table TSSOP SSOP SO DQ
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LVC selection table (cont.) TSSOP V
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Page 55 and 56:
ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107: Q100 Standard Logic functions & pac
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
Page 155 and 156: Toshiba one gate IDT logic TC7 S Z
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