Logic selection guide 2016

Recommendations

Info

LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVC169 Binary counter/ timer Presettable synchronous 4-bit binary up/down counter Suffix DGG, PW Suffix DC Suffix DB, DL Suffix D Suffix BQ, BX • • • • Suffix EC, EV Suffix GD, GF, GM, GN, GS, GT, GX 74LVC1G00 NAND gate Single 2-input NAND gate • • 74LVC1G02 NOR gate Single 2-input NOR gate • • 74LVC1G04 74LVC1G06 74LVC1G07 Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Suffix DP, GW, GV Single inverter • • Single inverter; open drain • • Single buffer; open drain • • 74LVC1G08 AND gate Single 2-input AND gate • • 74LVC1G10 NAND gate Single 3-input NAND gate • • 74LVC1G11 AND gate Single 3-input AND gate • • 74LVC1G123 74LVC1G126 Multivibrator Buffer/inverter/ driver Single retriggerable monostable multivibrator Single buffer/line driver (3-state) • • • • • 74LVC1G14 Schmitt trigger Single inverter Schmitt trigger • • 74LVC1G157 Digital multiplexer Single 2-input multiplexer • • 74LVC1G17 Schmitt trigger Single buffer Schmitt trigger • • 74LVC1G18 74LVC1G19 Decoder/ demultiplexer Decoder/ demultiplexer 1-to-2 demultiplexer (3-state) • • 1-to-2 decoder/demultiplexer • • 74LVC1G27 NOR gate Single 3-input NOR gate • • 74LVC1G3157 Analog switch Single-pole, double-throw analog switch • • 74LVC1G32 OR gate Single 2-input OR gate • • 74LVC1G332 OR gate Single 3-input OR gate • • 74LVC1G34 74LVC1G38 74LVC1G384 74LVC1G386 74LVC1G53 74LVC1G57 74LVC1G58 74LVC1G66 74LVC1G74 74LVC1G79 Buffer/inverter/ driver NAND gate Analog switch EXCLUSIVE-OR gate Analog switch Configurable multi-function gate Configurable multi-function gate Analog switch D-type flip-flop D-type flip-flop Single buffer • • Single 2-input NAND gate; open drain Single-pole, Single-throw analog switch Single 3-Input EXCLUSIVE-OR gate Single-pole, double-throw analog switch Configurable gate; Schmitt trigger Configurable gate; Schmitt trigger Single-pole, Single-throw analog switch Single D-type flip-flop with set and reset; positive-edge trigger Single D-type flip-flop; positive-edge trigger • • • • • • • • • • • • • • • • • • • • • • 50 NXP Logic selection guide 2016
LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVC1G80 74LVC1G86 74LVC1G97 74LVC1G98 74LVC1G99 74LVC1GU04 74LVC2244A 74LVC2245A 74LVC240A 74LVC241A 74LVC257A D-type flip-flop EXCLUSIVE-OR gate Configurable multi-function gate Configurable multi-function gate Configurable multi-function gate Buffer/inverter/ driver Buffer/inverter/ driver Transceiver Buffer/inverter/ driver Buffer/inverter/ driver Digital multiplexer Single D-type flip-flop; positive-edge trigger Single 2-input EXCLUSIVE-OR gate Configurable gate; Schmitt trigger Configurable gate; Schmitt trigger Configurable gate; Schmitt trigger Suffix DGG, PW Suffix DC Suffix DB, DL Suffix D Suffix BQ, BX Suffix EC, EV Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • • • • • • • • • • • • • • Single inverter; unbuffered • • • Octal buffer/line driver with 30 Ω termination resistors (3-state) Octal transceiver with 30 Ω termination resistors (3-state) Octal inverter/line driver (3-state) Octal buffer/line driver (3-state) Quad 2-input multiplexer (3-state) • • • • • • • • • • • • • • • • • • • • 74LVC27 NOR gate Triple 3-input NOR gate • • • • 74LVC273 74LVC2952A D-type flip-flop Transceiver Octal D-type flip-flop with reset; positive-edge trigger Octal registered transceiver with 30 Ω termination resistors (3-state) • • • • • • • • 74LVC2G00 NAND gate Dual 2-input NAND gate • • • • 74LVC2G02 NOR gate Dual 2-input NOR gate • • • • 74LVC2G04 74LVC2G06 74LVC2G07 Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Dual inverter • • • • Dual inverter; open drain • • • • Dual buffer; open drain • • • • 74LVC2G08 AND gate Dual 2-input AND gate • • • • 74LVC2G125 74LVC2G126 Buffer/inverter/ driver Buffer/inverter/ driver Dual buffer/line driver; TTL-enabled (3-state) Dual buffer/line driver; TTL-enabled (3-state) • • • • • • • • 74LVC2G14 Schmitt trigger Dual inverter Schmitt trigger • • • 74LVC2G17 Schmitt trigger Dual buffer Schmitt trigger • • • 74LVC2G240 74LVC2G241 Buffer/inverter/ driver Buffer/inverter/ driver Dual inverter/line driver (3-state) Dual buffer/line driver (3-state) • • • • • • • • 74LVC2G32 OR gate Dual 2-input OR gate • • • • 74LVC2G34 Buffer/inverter/ driver Dual buffer • • • • NXP Logic selection guide 2016 51
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49: LVC selection table (cont.) TSSOP V
Page 53 and 54: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102:
Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138:
SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140:
SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142:
SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144:
SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146:
SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148:
SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150:
SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152:
Design tools NXP is committed to ma
Page 153 and 154:
Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
show all

Logic selection guide 2016

Create successful ePaper yourself

Delete template?

Save as template?